多输出函数的化简和静态冒险.ppt

1 F1 A B C 0 1 3 F2 A B C 3 6 7 F1 A B A C F2 A B B C Multiple OutputMinimization多输出函数的化简 Wecanhandleacircuitwithnoutputsasnindependentsingle outputdesignproblems 2 A B A C AB BC Multiple OutputMinimization多输出函数的化简 3 F1 A B C 0 1 3 F2 A B C 3 6 7 F1 A B A B C F2 A B A B C 利用各输出共享的乘积项可减少与门的使用量 Multiple OutputMinimization多输出函数的化简 4 A B A BC AB Multiple OutputMinimization多输出函数的化简 5 4 5TimingHazards定时冒险 Hazard whensteady stateanalysispredictsthattheoutputshouldnotchange acircuit soutputmayproduceashortpulse glitch becauseofcircuitdelays 若后继负载电路是一个对脉冲敏感的电路 这种尖峰脉冲可能使负载电路发生误动作 6 StaticHazards静态冒险 Static 1Hazard Static 0Hazard mostlyexistsinAND ORcircuits steady stateanalysis output 1 actuallymayproducea 0 glitch steady stateanalysis output 0 actuallymayproducea 1 glitch Theoutputfunctioncanbesimplifiedas F A A 1 Theoutputfunctioncanbesimplifiedas F A A 0 mostlyexistsinOR ANDcircuits 7 Forexample F X Y Z XZ YZ StaticHazards静态冒险 WhenX Y 1 wehave F Z Z WhileZchanges thecircuitwouldproducestatic 1Hazard 8 消除冒险的方法 输出端并接一个滤波电容 增加了输出波形的上升时间和下降时间 使波形变坏 StaticHazards静态冒险 消除方法二 增加一致项 可利用卡诺图 F XZ YZ XY 9 若卡诺图中 圈与圈之间有相切现象 则可能出现静态冒险 消除方法 引入一致项 consensusterms 覆盖冒险输入对 FindingStaticHazardsUsingMaps F XY YZ F XY Z W Z WY XZ W XY YZ WXZ 10 由多级传输通道的不同延迟导致 可采用同步设计来消除 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 DynamicHazard动态冒险 Theoutputchangemorethanonceasaresultofasignalinputvariablechange 11 Chapter6CombinationallogicDesignPractices DocumentationStandardsCircuittimingMSIcombinationallogiccircuit 12 6 1DocumentationStandards 结构化的理念Specification 说明书 接口及功能描述BlockDiagram 方框图 主要功能模块及其互联SchematicDiagram 原理图 TimingDiagram 定时图 StructuredLogicDeviceDescription 结构化逻辑器件描述 CircuitDescription 电路描述 解释电路内部如何工作 13 GateSymbols门符号 14 EquivalentGateSymbols等效门符号 INVERTER BUFFER NAND AND OR NOR 15 SignalnamesandActiveLevels SignalNamesSignalnameshouldconveyassociatedinformation ActiveLevelsforsignalsactivehigh 高电平有效 ENactivelow 低电平有效 EN LActiveLevelsforPins Inversionbubblesindicateactive lowpins 给定逻辑功能只在符号框的内部发生 16 Buses总线 Abusisacollectionoftwoormorerelatedsignallines 两根或多根相关信号线的集合 Busname DATA 31 0 ADDR 15 0 Representation Figure6 16 6 1 17 AdditionalSchematicInformation附带图示信息 IncludingICtypes referencedesignators andpinnumberindicatedintheschematicdiagrams Figure6 17 ICTypes IC类型 74HCT00ReferenceDesignators 参考标志 U1 U2PinNumber 引脚编号 Figure6 18 常用标准SSI芯片引脚定义 18 6 2CircuitTiming PropagationDelay传播延迟 Thetimethatittakesforachangeattheinputofthepathtoproduceachangeattheoutputofthepath 19 6 2CircuitTiming PropagationDelay传播延迟 Thetimethatittakesforachangeattheinputofthepathtoproduceachangeattheoutputofthepath Table6 2 6 3 定时分析时 一般取最坏情况 即最大延迟 tpHL和tpLH可能不同 20 6 2CircuitTiming PropagationDelay传播延迟 Thetimethatittakesforachangeattheinputofthepathtoproduceachangeattheoutputofthepath Table6 274LS 21 6 2CircuitTiming TimingDiagram定时图 时序图 Delayisnormallymeasuredbetweenthecenterpointsoftransitions 22 6 2CircuitTiming TimingDiagram定时图 时序图 23 6 2CircuitTiming d0 d1 d1 TimingDiagram定时图 时序图 24 4 19 a c 4 61 1 Doesthereexistanyhazardineachcircuitcorrespondingtothefollowinglogicexpressions Ifso howtoeliminatethehazard