sigma-delta调制器论文：一种四阶带通sigma-delta调制器的分析与设计.doc

sigma-delta调制器论文：一种四阶带通sigma-delta调制器的分析与设计【中文摘要】高性能带通sigma-delta调制器是数字中频接收机的核心模块,它和数字降采样滤波器一起完成对中频信号的数字化处理。这样,信道选择和I/Q解调等操作在数字域完成,从而提高了接收机的设计灵活性,减小了电路的设计复杂度,因此成为射频通信领域的研究热点之一。本文基于0.18m CMOS工艺对一种四阶带通sigma-delta调制器进行了分析和设计。首先,本文介绍了带通sigma-delta调制器的原理和结构,确定设计方案一位四阶单环多路反馈结构,并在MATLAB/SIMULINK环境下对方案进行了行为级验证。仿真结果表明:峰值信噪比可达到90.5dB,满足设计要求。并基于此给出电路系统中关键模块的主要指标,对后期电路设计提供参考。其次,根据行为级建模提供的系数,基于TSMC0.18m工艺,采用1.8V电源,200倍的过采样率,80MHz的有效采样频率,对中心频率为20MHz、带宽为200KHz的四阶带通sigma-delta调制器进行了电路级设计,主要包括运算放大器、双延迟型谐振器、一位量化器、反馈延迟和一位DAC电路、时钟产生电路和基准电路。仿真结果表明:峰值信噪比为84.2dB,即有效转换位数为14位,静态功耗为18mW。最后,在电路设计的基础上,对四阶带通sigma-delta调制器进行了版图设计和后仿。其中版图有效面积为:0.7mm*0.4mm;后仿结果表明:信噪比为75dB,基本满足设计要求。【英文摘要】The bandpass sigma-delta modulator(BP DSM, for short) is the key block of the digital IF receiver. It digitizes the analog signal at an intermediate frequency, together with the digital decimation filter. Thus, the channel election and I/Q demodulation are operated in the digital domain. Then, the flexibility of the receiver is increased, and the complexity of the circuits-designing are relieved. So the bandpass sigma-delta modulator becomes one research focus in the field of RF communication. With the 0.18m CMOS technology, this paper analyzes and designs a fourth order bandpass sigma-delta modulator.Firstly, the theory and basic structure of sigma-delta modulator are introduced, and the system scheme of a fourth order one bit single-loop multi-feedback is brought forward. Then the behavior model and functionality validation is done in the environment of MATLAB/SIMULINK with the SDToolbox. The simulation results show that the peak SNR arrives 95dB, satisfying the requirement. Besides, the behavior model points out the specifications of the main blocks, providing reference for circuit-level designing.Then, the fourth order BP DSM is designed at circuit-level, with the TSMC0.18 technology and operates with a 1.8V supply voltage. It main consists of the operational amplifier, DD(double-delay) resonator, 1bit quantizer, delay feedback and 1bit DAC, clock signal generation circuit and bandgap reference circuit. The center frequency is 20MHz, the OSR is 200, the bandwidth is 200kHz,and the sampling frequency is 80MHz. The simulation results show that the SNR arrives 84.2dB i.e. the effective number of bit is 14bit, and the static power of the system is 18mW.Finally, biasing the circuit-level designing, the layout of the BP DSM is accomplished and the post-simulation is done. The effective area is 0.7*0.4mm2, and the post-simulation shows the SNR is 75dB.【关键词】sigma-delta调制器 谐振器 噪声整形技术 过采样技术 多路反馈【英文关键词】sigma-delta modulator resonator over-sampling noise-shaping multi-feedback【目录】一种四阶带通sigma-delta调制器的分析与设计摘要4-5Abstract5第1章 绪论8-141.1 课题背景及研究意义8-121.2 sigma-delta调制器的发展现状12-131.3 论文的研究内容及组织结构13-14第2章 sigma-delta调制器原理和系统结构设计14-302.1 sigma-delta调制器14-242.1.1 过采样技术15-172.1.2 噪声整形技术17-192.1.3 高阶sigma-delta调制器的结构设计19-242.2 行为级验证24-292.2.1 谐振器模型262.2.2 行为级模型和仿真结果26-292.3 本章小节29-30第3章 电路设计30-503.1 谐振器电路30-413.1.1 谐振器基本理论30-313.1.2 三种常见的谐振器类型31-363.1.3 谐振器中电容值的选取363.1.4 放大器电路36-403.1.5 栅压自举开关40-413.2 量化器电路41-423.3 反馈延时电路和 1bit DAC 电路42-433.4 时钟信号产生电路43-453.5