汉字点阵显示VHDL源程序.doc

汉字点阵显示VHDL源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity hzxs isport(clk1,clk2:in std_logic; rd:out std_logic; we: out std_logic; ledw:out std_logic_vector(2 downto 0);d:out std_logic_vector(0 downto 7); end hzxs;architecture hav of hzxs issignal count:std_logic_vector(0 to 2);signal a: std_logic_vector(3 downto 0);begin process(clk2)begin if clk2event and clk2=1 thencount=count+1;end if;ledw=count;a(2 downto 0)=count;end process;process(clk1)beginif clk1event and clk1=1 thena(3)ddddddddddddddddd=00000000;end case;end process;rd=1;we=0;end hav;数字抢答器VHDL源程序1）抢答器QDQlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity qdq isport(clr:in std_logic; a,b,c,d:in std_logic; an,bn,cn,dn:out std_logic); end qdq;architecture hav of qdq issignal ss:std_logic_vector(0 to 3);beginssan=1;bn=0;cn=0;dnan=0;bn=1;cn=0;dnan=0;bn=0;cn=1;dnan=0;bn=0;cn=0;dnan=0;bn=0;cn=0;dn=0;end case; elsif clr=0 thenan=0;bn=0;cn=0;dn=0;end if;end process;end hav;2）计分器JFQlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity jfq isport(en1:in std_logic; clk3:in std_logic; bs:out std_logic_vector(3 downto 0); ss:out std_logic_vector(3 downto 0); gs:out std_logic_vector(3 downto 0); add:in std_logic; dec:in std_logic);end jfq;architecture hav of jfq isbeginprocess(clk3,en1,add,dec)variable ssw:std_logic_vector(3 downto 0);variable bsw:std_logic_vector(3 downto 0);beginbsw:=0001;if clk3=1 and clk3event then if en1=1 then if add=1 then if ssw=1001 then bsw:=bsw+1; ssw:=0000; else ssw:=ssw+1; end if;elsif dec=1 then if ssw=1111 then bsw:=bsw-1; ssw:=1001; else ssw:=ssw-1; end if; end if;end if;end if;ss=ssw; bs=bsw; gs=0000;end process; end hav;3) 选择器XZQlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity xzq isport( a1,b1:in std_logic; abw:in std_logic_vector(0 to 3); asw:in std_logic_vector(0 to 3); agw:in std_logic_vector(0 to 3); bbw:in std_logic_vector(0 to 3); bsw:in std_logic_vector(0 to 3); bgw:in std_logic_vector(0 to 3); obw:out std_logic_vector(0 to 3); osw:out std_logic_vector(0 to 3); ogw:out std_logic_vector(0 to 3);end xzq;architecture hav of xzq isbeginprocess(a1,b1)begin if a1=1 and b1=0 thenobw=abw;osw=asw;ogw=agw; elsif a1=0 and b1=1 thenobw=bbw;osw=bsw;ogw=bgw; end if;end process;end hav;4）译码器YMQlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity ymq isport( clk2:in std_logic; bw:in std_logic_vector(3 downto 0); sw:in std_logic_vector(3 downto 0); gw:in std_logic_vector(3 downto 0); y:out std_logic_vector(7 downto 0); ledw:out std_logic_vector(2 downto 0);end ymq;architecture hav of ymq issignal knum:std_logic_vector(3 downto 0);signal count:std_logic_vector(2 downto 0);beginprocess(clk2)begin if clk2event and clk2=1 then if count2 then count=count+1;else count=000;end if;end if;end process;ledw=count;knum=gw when count=0 else sw when count=1 else bw when count=2 ;y=00111111 when knum=0000 else 00000110 when knum=0001 else 01011011 when knum=0010 else 01001111 when knum=0011 else 01100110 when knum=0100