EDA技术与VHDL期末复习程序汇总.pdf

1 目录 1 教材课后答案 2 3 2 If then 语句 4 选 1 选择器 P92 2 3 2 case 语句 4 选 1 选择器 P92 2 3 3 双 2 选 1 选择器 P92 2 3 4 1 1 位半减器 P92 2 3 4 2 用 1 位全减器 构成串行借位 8 位减法器 P92 3 3 5 含有上升沿 D 触发的时序电路 P92 3 3 6 根据图形写出程序 P92 4 3 7 异步清零和计数使能的 16 位二进制加减可控计数器 P92 4 5 2 例 5 5 是一个双进程 Mealy 状态机 将其改为单进程 比较输出波形 P174 5 5 3 序列检测器 P174 5 5 4 根据状态图写出程序 P176 7 7 3 用 WITH SELECT WHEN 语句描述 4 个 16 位至 1 个 16 位输出的 4 选 1 多路选择器 P248 8 7 7 将程序转换为 WITH SELECT 语句 P249 8 2 总结习题 9 1 优先级编码器 9 2 根据状态图写出程序 9 3 通用奇偶校验发生器电路 9 4 使用 loop 语句实现对输入矢量中连续出现的零的个数进行统计 10 5 设计一个对时钟进行 6 分频的电路 10 6 带 7 段数码显示的模 100 计数器 实现一个异步复位的模 100 累加计数器 11 7 信号发生器 12 8 设计一个自动售货机的控制器电路 13 9 设计一个含有 generic 的比较器 14 10 多位比较器 15 11 设计一个二 十进制 BCD 译码器 译码器输入 din 为 4 位二进制数 输出为 4 位二进制数表示的两个十进制 数 a b 15 12 串行数据接收器电路 16 13 设计一个计时器 它能从 0 秒计时到 9 分 59 秒 17 14 并 串转换器的电路 17 15 考试题型 18 3 课堂上补充的习题 18 1 简易 8 位桶形移位寄存器 18 2 序列检测器 19 3 计算输入矢量 16 个位 中的 1 的个数 19 4 交通灯控制器 20 2 1 教材课后答案教材课后答案 3 2 If then 语句语句 4 选选 1 选择器选择器 P92 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY mux41 IS PORT a b c d IN std logic s IN std logic vector 1 downto 0 y OUT std logic END ENTITY mux41 ARCHITECTURE one OF mux41 IS BEGIN PROCESS a b c d s BEGIN IF s 00 THEN y a elsif s 01 THEN y b elsif s 10 THEN y c elsif s 11 THEN y y y y y d end case end process end archmux 3 3 双双 2 选选 1 选择器选择器 P92 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY MUXK IS PORT a1 a2 a3 s0 s1 IN std logic outy OUT std logic END ENTITY MUXK ARCHITECTURE one OF MUXK IS signal tmp std logic BEGIN PROCESS a2 a3 s0 BEGIN IF s0 0 THEN tmp a2 ELSE tmp a3 END IF END PROCESS PROCESS a1 tmp s1 BEGIN IF s1 0 THEN outy a1 ELSE outy tmp END IF END PROCESS END ARCHITECTURE one 3 4 1 1 位位半半减器减器 P92 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY h suber IS PORT x y IN STD LOGIC s out diff OUT STD LOGIC END ENTITY h suber ARCHITECTURE fh1 OF h suber is SIGNAL abc STD LOGIC VECTOR 1 DOWNTO 0 BEGIN abc diff 0 s out diff 1 s out diff 1 s out diff 0 s out NULL END CASE END PROCESS END ARCHITECTURE fh1 3 3 4 2 用用 1 位全减器 构成串行借位位全减器 构成串行借位 8 位减法器位减法器 P92 LIBRARY IEEE 或门逻辑描述 USE IEEE STD LOGIC 1164 ALL ENTITY or2a IS PORT a b IN STD LOGIC c OUT STD LOGIC END ENTITY or2a ARCHITECTURE one OF or2a IS BEGIN c x y y s out e diff d u2 h suber PORT MAP x d y sub in s out f diff diffr u3 or2a PORT MAP a e b f c s out END ARCHITECTURE fd1 LIBRARY IEEE 8 位二进制全减器顶层设计描述位二进制全减器顶层设计描述 USE IEEE STD LOGIC 1164 ALL ENTITY suber 8 IS PORT x y IN STD LOGIC VECTOR 7 downto 0 sub in IN STD LOGIC diff OUT STD LOGIC VECTOR 7 downto 0 sub out OUT STD LOGIC END ENTITY suber 8 ARCHITECTURE fd8 OF suber 8 IS COMPONENT suder 调用半加器声明语句 PORT x y sub in IN STD LOGIC s out diffr OUT STD LOGIC END COMPONENT SIGNAL s0 s1 s2 s3 s4 s5 s6 STD LOGIC BEGIN U0 suder PORT MAP x x 0 y y 0 sub in sub in s out s0 diffr diff 0 U1 suder PORT MAP x x 1 y y 1 sub in s0 s out s1 diffr diff 1 U2 suder PORT MAP x x 2 y y 2 sub in s1 s out s2 diffr diff 2 U3 suder PORT MAP x x 3 y y 3 sub in s2 s out s3 diffr diff 3 U4 suder PORT MAP x x 4 y y 4 sub in s3 s out s4 diffr diff 4 U5 suder PORT MAP x x 5 y y 5 sub in s4 s out s5 diffr diff 5 U6 suder PORT MAP x x 6 y y 6 sub in s5 s out s6 diffr diff 6 U7 suder PORT MAP x x 7 y y 7 sub in s6 s out sub out diffr diff 7 END ARCHITECTURE fd8 3 5 含有上升沿含有上升沿 D 触发的时序电路触发的时序电路 P92 library ieee USE IEEE STD LOGIC 1164 ALL entity dff1 is PORT CLK0 IN STD LOGIC CL IN STD LOGIC OUT1 OUT STD LOGIC end ARCHITECTURE bhv OF dff1 IS SIGNAL Q D STD LOGIC begin D CL NAND Q PROCESS CLK0 CL begin IF CLK0 EVENT AND CLK0 1 THEN Q D end if end process OUT1 Q end bhv 4 3 6 根据图形写出程序 根据图形写出程序 P92 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY MX3256 IS PORT INA INB INC INCK IN STD LOGIC E OUT1 OUT STD LOGIC END ENTITY MX3256 ARCHITECTURE ONE OF MX3256 IS COMPONENT LK35 PORT A1 A2 CLK IN STD LOGIC O1 O2 OUT STD LOGIC END COMPONENT SIGNAL A B S Q STD LOGIC BEGIN U0 LK35 PORT MAP INA INB INCK B S U1 LK35 PORT MAP S Q INCK A OUT1 END ARCHITECTURE ONE 3 7 异步清零和计数使能的异步清零和计数使能的 16 位二进制加减可控计数位二进制加减可控计数 器器 P92 library IEEE use IEEE STD LOGIC 1164 all use IEEE STD LOGIC unsigned all entity counter4 is port clk in STD LOGIC clr in STD LOGIC en in STD LOGIC up down in STD LOGIC c out STD LOGIC DOUT buffer STD LOGIC VECTOR 16 downto 0 end counter4 architecture rtl of counter4 is begin process clk clr en up down begin if clr 1 then 异步清零 DOUT 0000 elsif en 1 then 异步计数使能 if clk event and clk 1 then if up down 1 then 加计数 if DOUT 1111 then c 1 DOUT 0000 else DOUT DOUT 1 c 0 end if else 减计数 if DOUT 0000 then c 1 DOUT 1111 else DOUT DOUT 1 c 0 end if end if end if end if end process end rtl 5 5 2 例例 5 5 是一个双进程是一个双进程 Mealy 状态机 将其改为单进状态机 将其改为单进 程 比较输出波形 程 比较输出波形 P174 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY MEALY12 IS PORT CLK DATAIN RESET IN STD LOGIC Q OUT STD LOGIC VECTOR 4 DOWNTO 0 END MEALY12 ARCHITECTURE behav OF MEALY12 IS TYPE states IS st0 st1 st2 st3 st4 SIGNAL STX states BEGIN COMREG PROCESS CLK RESET BEGIN IF RESET 1 THEN STX IF DATAIN 1 THEN STX st1 Q 10000 else Q IF DATAIN 0 THEN STX st2 Q 10111 else Q IF DATAIN 1 THEN STX st3 Q 10101 else Q IF DATAIN 0 THEN STX st4 Q 11011 else Q IF DATAIN 1 THEN STX st0 Q 11101 else Q STX st0 Q 00000 END CASE END IF END PROCESS COMREG END behav 例 5 5 双进程时序图 单进程时序图 5 3 序列检测器 序列检测器 P174 要求一 要求一 表达的是 moore 型状态机 特点是输出仅为当前状态的 函数 完成对序列数 11100101 的检测 当这一串序列数高位 在前 左移 串行进入检测器后 若此数与预置的密码数 相同 则输出 A 否则仍然输出 B 在检测过程中 任何一位不相等都将回到初始状态重新开始检测 要求二 要求二 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY SCHK IS PORT DIN CLK CLR IN STD LOGIC AB OUT STD LOGIC VECTOR 3 DOWNTO 0 END SCHK ARCHITECTURE my arch OF SCHK IS TYPE state IS zero one two three four five six seven eight SIGNAL d STD LOGIC VECTOR 7 DOWNTO 0 SIGNAL pr state nx state state BEGIN d 11100101 Lower section PROCESS CLR clk BEGIN IF CLR 1 THEN pr state zero ELSIF clk EVENT AND clk 1 THEN pr state AB 1011 6 IF DIN d 7 THEN nx state one ELSE nx state AB 1011 IF DIN d 6 THEN nx state two ELSE nx state AB 1011 IF DIN d 5 THEN nx state three ELSE nx state AB 1011 IF DIN d 4 THEN nx state four ELSE nx state AB 1011 IF DIN d 3 THEN nx state five ELSE nx state AB 1011 IF DIN d 2 THEN nx state six ELSE nx state AB 1011 IF DIN d 1 THEN nx state seven ELSE nx state AB 1011 IF DIN d 0 THEN nx state eight ELSE nx state AB 1010 nx state zero END CASE END PROCESS END my arch 要求三 要求三 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY SCHK IS PORT DIN CLK CLR IN STD LOGIC 串行输入数据位 工作时钟 复位信号 d STD LOGIC VECTOR 7 DOWNTO 0 AB OUT STD LOGIC VECTOR 3 DOWNTO 0 检测结果输出 END SCHK ARCHITECTURE my arch OF SCHK IS TYPE state IS zero one two three four five six seven eight SIGNAL c state state BEGIN d 11100101 PROCESS CLR clk BEGIN IF CLR 1 THEN c state zero AB AB 1011 IF DIN d 7 THEN c state one ELSE c state AB 1011 IF DIN d 6 THEN c state two ELSE c state AB 1011 IF DIN d 5 THEN c state three ELSE c state AB 1011 IF DIN d 4 THEN c state four ELSE c state AB 1011 IF DIN d 3 THEN c state five ELSE c state AB 1011 IF DIN d 2 THEN c state six ELSE c state AB 1011 IF DIN d 1 THEN c state seven ELSE c state AB 1011 IF DIN d 0 THEN c state eight ELSE c state AB 1010 c state zero END CASE END IF END PROCESS END my arch 5 4 根据状态图写出程序根据状态图写出程序 P176 单进程 单进程 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY SCHK5 4 IS PORT CLK reset IN STD LOGIC ina IN STD LOGIC VECTOR 2 DOWNTO 0 outa OUT STD LOGIC VECTOR 3 DOWNTO 0 END SCHK5 4 ARCHITECTURE my arch OF SCHK5 4 IS TYPE state IS s0 s1 s2 s3 SIGNAL c state state BEGIN PROCESS CLK reset BEGIN IF reset 1 THEN c state IF ina 101 THEN c state s1 outa 0010 ELSif ina 111 THEN c state s0 outa outa 1001 IF ina 110 THEN c state s2 ELSif ina 000 THEN c state outa 1111 IF ina 100 THEN c state s3 ELSif ina 100 THEN c state IF ina 101 THEN c state s0 outa 1101 ELSif ina 011 THEN c state s3 outa 1110 END IF END CASE END IF END PROCESS END my arch 双进程 双进程 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY SCHK5 4 IS PORT CLK reset IN STD LOGIC ina IN STD LOGIC VECTOR 2 DOWNTO 0 outa OUT STD LOGIC VECTOR 3 DOWNTO 0 END SCHK5 4 ARCHITECTURE my arch OF SCHK5 4 IS TYPE state IS s0 s1 s2 s3 SIGNAL pr state nx state state BEGIN PROCESS CLK reset BEGIN IF reset 1 THEN pr state s0 ELSIF clk EVENT AND clk 1 THEN pr state IF ina 101 THEN nx state s1 outa 0010 ELSif ina 111 THEN nx state s0 outa outa 1001 IF ina 110 THEN nx state s2 ELSif ina 000 THEN nx state outa 1111 IF ina 100 THEN nx state s3 ELSif ina 100 THEN nx state IF ina 101 THEN nx state s0 outa 1101 ELSif ina 011 THEN nx state s3 outa 1110 END IF END CASE END PROCESS END my arch 7 3 用用 WITH SELECT WHEN 语句描述语句描述 4 个个 16 位至位至 1 个个 16 位输出的位输出的 4 选选 1 多路选择器 多路选择器 P248 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY mux1641 IS PORT a b c d IN STD LOGIC vector 15 downto 0 sel IN STD LOGIC vector 1 downto 0 dataout OUT STD LOGIC vector 15 downto 0 END mux1641 ARCHITECTURE concunt OF mux1641 IS BEGIN WITH sel SELECT dataout a WHEN 00 b WHEN 01 c WHEN 10 d WHEN 11 ZZZZZZZZZZZZZZZZ WHEN OTHERS END concunt 7 7 将程序转换为将程序转换为 WITH SELECT 语句 语句 P249 改前改前 PROCESS a b c d BEGIN IF a 0 AND b 1 THEN next1 1101 ELSIF a 0 THEN next1 d ELSIF b 1 THEN next1 c ELSE Next1 1011 END IF END PROCESS 改后改后 next1 1101 WHEN a 0 AND b 1 ELSE d WHEN a 0 ELSE c WHEN b 1 ELSE 1011 9 2 总结习题总结习题 1 优先级编码器 优先级编码器 图是一个 7 级优先级编码器 如果输入矢量中出现多个 1 那么电路将优先对 最高位编码输出 000 表示输入矢量中没有出现 位 1 不需要编码输出 使用 WHEN ELSE 语句实 现该电路 LIBRARY ieee USE ieee std logic 1164 all ENTITY encoder IS PORT x IN bit VECTOR 7 DOWNTO 1 y OUT bit VECTOR 2 DOWNTO 0 END encoder ARCHITECTURE encoder1 OF encoder IS BEGIN y 111 WHEN x 7 1 ELSE 110 WHEN x 6 1 ELSE 101 WHEN x 5 1 ELSE 100 WHEN x 4 1 ELSE 011 WHEN x 3 1 ELSE 010 WHEN x 2 1 ELSE 001 WHEN x 1 1 ELSE 000 END encoder1 2 根据状态图写出程序根据状态图写出程序 library ieee use ieee std logic 1164 all entity fsm is port inp rst clk in std logic outp out std logic vector 1 downto 0 end fsm architecture arch of fsm is type state is state1 state2 state3 state4 signal pr state nx state state signal temp std logic vector 1 downto 0 begin process rst clk begin if rst 1 then pr state state1 elsif clk event and clk 1 then outp temp pr state temp 00 if inp 1 then nx state state2 else nx state temp 01 if inp 0 then nx state state3 else nx statetemp 10 if inp 1 then nx state state4 else nx statetemp 11 if inp 1 then nx state state1 else nx state state2 end if end case end process end arch 3 通用奇偶校验发生器电路 通用奇偶校验发生器电路 当输入矢量中 1 的个数分别为奇数和偶数时 所增 加的输出位的值相应地为 1 和 0 这样使得输出矢量中 1 的个数恒为偶数 ENTITY parity gen IS GENERIC n INTEGER 7 PORT input IN BIT VECTOR n 1 DOWNTO 0 10 output OUT BIT VECTOR n DOWNTO 0 END parity gen ARCHITECTURE parity OF parity gen IS BEGIN PROCESS input VARIABLE temp1 BIT VARIABLE temp2 BIT VECTOR output RANGE BEGIN temp1 0 FOR i IN input RANGE LOOP temp1 temp1 XOR input i temp2 i input i END LOOP temp2 output HIGH temp1 output count count 1 WHEN OTHERS EXIT END CASE END LOOP zeros count END PROCESS END behavior 5 设计一个对时钟进行设计一个对时钟进行 6 分频的电路分频的电路 LIBRARY ieee USE ieee std logic 1164 all ENTITY freq divider IS PORT clk IN STD LOGIC out1 out2 BUFFER STD LOGIC end freq divider ARCHITECTURE example OF freq divider IS SIGNAL count1 INTEGER RANGE 0 TO 7 BEGIN PROCESS clk VARIABLE count2 INTEGER RANGE 0 TO 7 BEGIN IF clk EVENT AND clk 1 THEN count1 count1 1 count2 count2 1 IF count1 2 THEN out1 NOT out1 count1 0 END IF IF count2 3 THEN out2 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 NULL END CASE CASE temp2 IS WHEN 0 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 digit1 NULL END CASE END PROCESS END counter 12 7 信号发生器 信号发生器 ENTITY sig IS PORT clk IN BIT out1 out2 buffer BIT END sig ARCHITECTURE sig OF sig IS TYPE state IS one two three four SIGNAL pr state1 nx state1 state SIGNAL pr state2 nx state2 state SIGNAL pr state3 nx state3 state SIGNAL out3 out4 out5 BIT BEGIN PROCESS clk BEGIN IF clk EVENT AND clk 1 THEN pr state1 nx state1 END IF END PROCESS PROCESS clk BEGIN IF clk EVENT AND clk 1 THEN pr state2 nx state2 END IF END PROCESS PROCESS clk BEGIN IF clk EVENT AND clk 0 THEN pr state3 out1 1 nx state1 out1 0 nx state1 out1 0 nx state1 out1 0 nx state1 out3 0 nx state2 out3 1 nx state2 out3 0 nx state2 out3 0 nx state2 out4 0 nx state3 out4 1 nx state3 out4 0 nx state3 out4 0 nx state3 one END CASE END PROCESS out5 out3 and out4 out2 out1 or out5 end sig 13 8 设计一个自动售货机的控制器电路 设计一个自动售货机的控制器电路 该自动售货机销售价格为 25 美分的糖果 控制器的输入和输出如图所示 输入信号是 nickel in 投入 5 美分 dime in 投入 10 美分 和 quarter in 存放 25 美分 另外两个必要的输入 是 clk 时钟 和 rst 复位 控制器相应地有 3 个输出 candy out 用于控制发放糖果 nickel out 用于控制找回 5 美分的零钱 dime out 用于控制找回 10 美分零钱 LIBRARY ieee USE ieee std logic 1164 all ENTITY vending machine IS PORT clk rst IN STD LOGIC nickel in dime in quarter in IN BOOLEAN candy out nickel out dime out out std logic END vending machine ARCHITECTURE fsm OF vending machine IS TYPE state IS st0 st5 st10 st15 st20 st25 st30 st35 st40 st45 SIGNAL present state next state STATE BEGIN Lower section of the FSM Sec 8 2 PROCESS rst clk BEGIN IF rst 1 THEN present state st0 ELSIF clk EVENT AND clk 1 THEN present state candy out 0 nickel out 0 dime out 0 IF nickel in THEN next state st5 ELSIF dime in THEN next state st10 ELSIF quarter in THEN next state st25 ELSE next state candy out 0 nickel out 0 dime out 0 IF nickel in THEN next state st10 ELSIF dime in THEN next state st15 ELSIF quarter in THEN next state st30 ELSE next state candy out 0 nickel out 0 dime out 0 IF nickel in THEN next state st15 ELSIF dime in THEN next state st20 ELSIF quarter in THEN next state st35 ELSE next state candy out 0 nickel out 0 dime out 0 14 IF nickel in THEN next state st20 ELSIF dime in THEN next state st25 ELSIF quarter in THEN next state st40 ELSE next state candy out 0 nickel out 0 dime out 0 IF nickel in THEN next state st25 ELSIF dime in THEN next state st30 ELSIF quarter in THEN next state st45 ELSE next state candy out 1 nickel out 0 dime out 0 next state candy out 1 nickel out 1 dime out 0 next state candy out 1 nickel out 0 dime out 1 next state candy out 0 nickel out 1 dime out 0 next state candy out 0 nickel out 0 dime out 1 next state d2 f1 d1 d2 f1 d1d2 then f1 1 else f1 0 end if if d1 d2 then f2 1 else f2 0 end if if d1 d2 then f3 1 else f3 B then Y 001 elsif A B then Y 010 else Y 100 end if end process end rtl 11 设计一个二 设计一个二 十进制十进制 BCD 译码器 译码器输入译码器 译码器输入 din 为为 4 位二进制数 输出为位二进制数 输出为 4 位二进制数表示的两个位二进制数表示的两个十进十进 制数制数 a b library ieee use ieee std logic 1164 all use ieee std logic signed all entity v2 bcdymq is port din in integer range 15 downto 0 a b out integer range 9 downto 0 end architecture fpq1 of v2 bcdymq is begin p1 process begin if din 10 then a din b 0 else a din 1 10 b 0 temp 0 err 0 data vaild 0 ELSIF clk EVENT AND clk 1 THEN IF reg 0 0 AND din 1 THEN reg 0 1 ELSIF reg 0 1 THEN count count 1 IF count 10 THEN reg count din ELSIF count 10 THEN temp reg 1 XOR reg 2 XOR reg 3 XOR reg 4 XOR reg 5 XOR reg 6 XOR reg 7 XOR reg 8 OR NOT reg 9 err temp count 0 reg 0 din IF temp 0 THEN data vaild 1 data reg 7 DOWNTO 1 END IF END IF END IF END IF END PROCESS END rtl 17 13 设计一个计时器 它能从 设计一个计时器 它能从 0 秒计时到秒计时到 9 分分 59 秒秒 见 图 当前时间可以在 SSD 7 段数码显示器 上显示 要求电路具有启动和复位按钮 时钟频率为 1 Hz LIBRARY ieee USE ieee std logic 1164 all ENTITY fen IS PORT clk reset start IN STD LOGIC s1 s2 m1 OUT integer range 0 to 10 END fen ARCHITECTURE counter OF fen IS BEGIN PROCESS clk reset start VARIABLE ts2 ts1 tm1 INTEGER RANGE 0 TO 10 BEGIN counter IF reset 1 THEN ts1 0 ts2 0 tm1 0 elsif start 1 then IF clk EVENT AND clk 1 THEN ts1 ts1 1 IF ts1 10 THEN ts1 0 ts2 ts2 1 IF ts2 6 THEN ts2 0 tm1 tm1 1 IF tm1 10 THEN tm1 0 end if END IF END IF end if END IF s1 ts1 s2 ts2 m1 tm1 END PROCESS END counter 14 并 并 串转换器的电路串转换器的电路结构如图所示 d 7 0 是需要发 送的并行数据 dout 上是真正串行输出的数据 另外还 有两个输入 clk 和 load 当 load 有效时 并行输入数 据 d 7 0 被同步存储在移位寄存器中 当 load 保持为高 时 MSB 即 d 7 在输出端始终保持有效 一旦 load 返 回 0 接下来移位寄存器的各个位将在每个时钟上升沿 依次出现在输出端口 dout 上 8 位数据全部发送完毕之 后 输出端在下一次数据传输之前一直保持为低电平 LIBRARY ieee USE ieee std logic 1164 all ENTITY serial converter IS PORT d IN STD LOGIC VECTOR 7 DOWNTO 0 clk load IN STD LOGIC dout OUT STD LOGIC END serial converter ARCHITECTURE serial converter OF serial converter IS SIGNAL reg STD LOGIC VECTOR 7 DOWNTO 0 BEGIN PROCESS clk BEGIN IF clk EVENT AND clk 1 THEN IF load 1 THEN reg d ELSE reg reg 6 DOWNTO 0 END IF END IF END PROCESS dout reg 7 END serial converter 18 15 考试题型考试题型 library ieee use ieee std logic 1164 all ENTITY adder IS PORT A B Cin IN STD LOGIC sum Co OUT STD LOGIC END adder ARCHITECTURE behavior OF adder IS SIGNAL s STD LOGIC BEGIN s A xor B sum s xor cin Co s and Cin or A and B END behavior library ieee use ieee std logic 1164 all entity adder8 is port A in std logic vector 7 downto 0 B in std logic vector 7 downto 0 Cin in std logic Co out std logic sum out std logic vector 7 downto 0 end adder8 architecture structure of adder8 is component 1 port A in std logic B in std logic Cin in std logic Co out std logic sum out std logic end component signal carry std logic vector 8 downto 0 begin carry 0 Cin adder1 for i in 0 to 7 2 adderx adder 3 A i B i carry i carry i 1 sum i end generate adder1 Co carry 8 end structure 1 在程序的空白处填入适当的语句使程序完整 1 2 3 2 说明此程序实现的功能 3 课堂上补充的习题课堂上补充的习题 1 简易简易 8 位桶形移位寄存器位桶形移位寄存器 LIBRARY ieee USE ieee std logic 1164 all ENTITY barrel IS PORT inp IN std logic vector 7 downto 0