多功能数字时钟.doc

一、实验任务及要求1. 能进行正常的时、分、秒计时功能，分别由6个数码管显示24小时、60分钟、60秒钟的计数器显示。2. 能进行闹钟的时、分、秒的设置，分别由6个数码管显示24小时、60分钟、60秒钟的闹钟显示。3. 当“mode”为“1”时，6个数码管显示显示正常计时状态，当“mode”为“0”时，6个数码管显示显示闹钟状态。4. 能利用实验系统上的按键实现计时状态下的“校时”与“校分”功能：(1) 当“set_hour”为“1”时，每次按动“k_hour”键一次，“小时”+1，若一秒内未按动“k_hour”键则小时以4Hz的频率递增计数，并按24小时循环，计满23小时后在回00；(2) 当“set_minute”为“1”时，每次按动“k_minute”键一次，“分钟”+1，若一秒内未按动“k_minute”键则分钟以4Hz的频率递增计数，并按60分钟循环，计满分钟后回00；(3) 按下“reset”键时，“小时”，“分钟”，“秒”清零；5. 能用实验系统上的按键实现闹钟下的“校时”与“校分”功能：(4) 当“set_hour_alarm每次按动“k_hour_alarm”键一次，“小时”+1，若一秒内未按动“k_hour_alarm”键则小时以4Hz的频率递增计数，并按24小时循环，计满23小时后在回00；(5) 当“set_minute_alarm”为“1”时，每次按动“k_minute_alarm”键一次，“分钟”+1，若一秒内未按动“k_minute_alarm”键则分钟以4Hz的频率递增计数，并按60分钟循环，计满分钟后回00；6. 能利用蜂鸣器做整点报时：(1) 当计时到达5950时开始报时，在5951、53、55、57鸣叫，鸣叫频率可为512Hz；(2) 到达5959时发频率为1024Hz的高音，结束时为整点。7. 能利用蜂鸣器做闹钟报时：当闹钟定时时间到时，蜂鸣器发出周期为1s的滴、滴声，持续时间为10s；8. 用层次化设计方法设计该电路，用VHDL语言编写各个功能模块。9. 报时功能、闹时功能用功能仿真的方法验证，可通过观察有关波形确认电路设计是否正确。10. 完成电路设计后，用实验系统下载验证。 二、设计说明与论述系统顶层框图计数控制 模块 调时 调分 计时时间显示输出 整点报时控制 reset clk 蜂鸣器输出动态显示 模块 时间 显示闹钟控制 模块 调时 调分 闹钟时间显示输出 闹钟报时控制 reset clk 蜂鸣器输出整点报时模块 clk分频器 模块 1024Hz sound sound 1024Hz 512Hz 时间 4Hz 闹钟报时模块 1Hz clk sound 时间模块电路功能如下：1. 输出显示由秒计数器、分计数器、时计数器组成。；2. 输入频率为1024hz，经过分频器分出1024Hz,512Hz,4Hz,1Hz信号驱动电路；3. 前五声讯响功能报时电路由500Hz驱动，整点报时有1024hz驱动。4. 闹时电路模块也需要500Hz或1KHz音频信号以及来自秒计数器、分计数器和时计数器的输出信号作本电路的输入信号。三.状态图ASM图与MDS图开始 Mode_in 1 0 Mode=0Mode=10 0 hour_inhour_in_1 1 Set_hout_1=1K_hour_1=h1Set_hout=1K_hour=hminute_in_1minute_in0 1 0 1 Set_miute_1=1K_minute_1=h1Set_minute=1K_minute=hReset_in0 1Reset=1 Mode=1 mode=0S5S1 Mode=0 Mode=1 Set_hour=1 set_hour_1=1 set_hour_1=0 Set_hour=0S6S2 Set_minute=0 Set_minute=1 set_minute_1=1 Set_minute_1=0S7S3reset=0 Resert=1S4四、各功能模块设计及源程序；1. 正常计时功能模块1）秒计时LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second is port( clk,reset,set_minute:INSTD_LOGIC; enmin:out STD_LOGIC; daout:out std_logic_vector (6 downto 0);end second ;ARCHITECTURE fun OF second ISsignal count:std_logic_vector (6 downto 0);signal enmin_1,enmin_2:std_logic;begin daout=count; enmin=(enmin_1 or (not set_minute);process(clk,reset)begin if(reset=0)then count =0000000; elsif( clkevent and clk=1) then if(count (3 downto 0) =1001)then if(count16#60#) then if(count=1011001) then enmin_1=1; count=0000000; else count=count+7; end if; else count=0000000; end if; elsif(count16#60#) then count=count+1; enmin_1=0; else count=0000000; end if; end if;end process;end fun;2）分钟计时LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute is port( clk,reset,set_hour:INSTD_LOGIC; enhour:out STD_LOGIC; daout:out std_logic_vector (6 downto 0);end minute;ARCHITECTURE fun OF minute ISsignal count:std_logic_vector (6 downto 0);signal enhour_1,enhour_2:std_logic;begin daout=count; enhour=(enhour_1 or (not set_hour);process(clk,reset)begin if(reset=0)then count =0000000; elsif( clkevent and clk=1) then if(count (3 downto 0) =1001)then if(count16#60#) then if(count=1011001) then enhour_1=1;count=0000000; else count=count+7; end if; else count=0000000; end if; elsif(count16#60#) then count=count+1; enhour_1=0; else count=0000000; end if; end if;end process;end fun; 3）小时计时LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour is port( clk,reset:INSTD_LOGIC; daout:out std_logic_vector (5 downto 0);end hour ;ARCHITECTURE fun OF hour ISsignal count:std_logic_vector (5 downto 0);begin daout=count;process(clk,reset)begin if(reset=0)then count =000000; elsif( clkevent and clk=1) then if(count (3 downto 0) =1001)then if(count 16#23#) then count= count+7; else count=000000; end if; elsif(count16#23#) then count=count+1; else count=000000; end if; end if;end process;end fun;2. 正常闹钟功能模块1） 秒计时LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity second_1 is port( set_minute:INSTD_LOGIC; enmin:out STD_LOGIC; daout:out std_logic_vector (6 downto 0);end second_1 ;ARCHITECTURE fun OF second_1 ISsignal count:std_logic_vector (6 downto 0);begin enmin=(not set_minute); daout=0000000;end fun;2） 分钟计时LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity minute_1 is port( clk_4,set_minute:INSTD_LOGIC; set_hout:in STD_LOGIC; enhour:out STD_LOGIC; daout:out std_logic_vector (6 downto 0);end minute_1;ARCHITECTURE fun OF minute_1 ISsignal count:std_logic_vector (6 downto 0);signal clk_minute:std_logic;begin daout=count; enhour=(not set_hout); clk_minute=clk_4 OR set_minute;process(clk_minute)beginif ( clk_minuteevent and clk_minute=1)then if(count (3 downto 0) =1001)then if(count16#60#) then if(count=1011001) then count=0000000; else count=count+7; end if; else count=0000000; end if; elsif(count16#60#) then count=count+1; else count=0000000; end if; end if;end process ;end fun;3） 小时计时LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour_1 is port( clk_4,set_hour:INSTD_LOGIC; daout:out std_logic_vector (5 downto 0);end hour_1 ;ARCHITECTURE fun OF hour_1 ISsignal count:std_logic_vector (5 downto 0);signal clk_hour:std_logic;begin daout=count; clk_hour=clk_4 OR set_hour;process(clk_hour)beginif( clk_hourevent and clk_hour=1) then if(count (3 downto 0) =1001)then if(count 16#23#) then count= count+7; else count=000000; end if; elsif(count16#23#) then count=count+1; else count=000000; end if; end if;end process;end fun;3. 动态显示模块1） 模六计数器LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;ENTITY six ISPORT( reset,clk : INSTD_LOGIC; q: OUTSTD_LOGIC_vector(2 downto 0);END six;ARCHITECTURE behav OF six IS signal qo:integer range 0 to 5;BEGIN Process (clk,reset,qo) begin if reset=0 then qo=0; elsif(clkevent and clk=1) then if qo=5 then qo=0; else qo=qo+1; end if; end if;qDAOUT(3 DOWNTO 2)=00 ;DAOUT(1 DOWNTO 0)DAOUTDAOUT(3)=0; DAOUT(2 DOWNTO 0)DAOUTdaout(3)=0; daout (2 downto 0) DAOUTledledledledledledledledledledled=XXXXXXX;end case;end process; end fun;4. 分频器 LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fen is port( clk:in STD_LOGIC; clk_1024,clk_512,clk_4,clk_1:out STD_LOGIC);end fen ;ARCHITECTURE behave OF fen ISbeginprocess(clk)variable count: integer range 0 TO 1;begin if clkevent and clk=1 then if count1 then count:=count+1; clk_512=0; else count:=0; clk_512=1; end if;end if; end process;process(clk)variable count_1:integer range 0 TO 255 ;begin if clkevent and clk=1 then if count_1255 then count_1:=count_1+1; clk_4=0; else count_1:=0; clk_4=1; end if;end if; end process;process(clk)variable count_2:integer range 0 TO 1023 ;begin if clkevent and clk=1 then if count_21023 then count_2:=count_2+1; clk_1=0; else count_2:=0; clk_1=1; end if;end if;end process;process(clk)begin clk_1024=clk; end process;end behave;5. 小时与分钟比较器LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_ARITH.all;entity vs_time is port( min,min_1 : in std_logic_vector (6 downto 0); hour,hour_1: in std_logic_vector (5 downto 0); key: out std_logic); end vs_time ;ARCHITECTURE fun OF vs_time ISsignal vs:std_logic;begin key= vs; process (min,min_1,hour,hour_1) begin if hour=hour_1 then if min-0000001=min_1-0000001 then vs=1; else vs=0; end if; else vs=0; end if;end process; end fun;6. 计时与闹钟显示选择器LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;ENTITY mux2_1 ISPORT( mode : INSTD_LOGIC;in_2: inSTD_LOGIC_vector(2 downto 0); in_3: inSTD_LOGIC_vector(3 downto 0); in_2_1: inSTD_LOGIC_vector(2 downto 0); in_3_1: inSTD_LOGIC_vector(3 downto 0);out_2: outSTD_LOGIC_vector(2 downto 0); out_3: outSTD_LOGIC_vector(3 downto 0);END mux2_1;ARCHITECTURE rt1 OF mux2_1 ISBEGIN PROCESS(mode,in_2,in_3,in_2_1,in_3_1) BEGIN IF(mode=1) THEN out_2=in_2; out_3=in_3;ELSE out_2=in_2_1; out_3=in_3_1; END IF;END PROCESS;END rt1;7. 整点报时器LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity al_zheng is port( clk_512,clk_1024:in STD_LOGIC; second,minute:in std_logic_vector (6 downto 0); sound:out STD_LOGIC);end al_zheng;ARCHITECTURE fun OF al_zheng isBeginprocess(clk_512,clk_1024,second,minute)begin if minute=1011001 then if second=1010001 or second=1010011 or second=1010101 or second=1010111 then sound=clk_512; elsif second=1011001 then sound=clk_1024; else sound=0; end if; else sound=0; end if;end process; end fun;8.闹钟报时器LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity al_bao is port( key:INSTD_LOGIC; clk_512:in STD_LOGIC; second:in std_logic_vector (6 downto 0); sound:out STD_LOGIC);end al_bao ;ARCHITECTURE fun OF al_bao ISsignal count:std_logic_vector(3 downto 0);beginprocess(key,clk_512)begin if key=1 then if second1011 then sound=clk_512; else sound=0; end if; end if; end process; end fun;9.控制器LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity controler is port( mode_in,hour_in,minute_in,hour_in_1,minute_in_1,reset_in:INSTD_LOGIC; k:in STD_LOGIC; set_hour,set_minute,set_hour_1,set_minute_1,k_hour,k_minute,k_hour_1,k_minute_1:out std_logic; mode,reset:out STD_LOGIC);end controler;ARCHITECTURE fun OF controler ISsignal a:std_logic;beginprocess(mode_in,hour_in,minute_in,hour_in_1,minute_in_1,reset_in,k)beginset_hour=0;set_minute=0;set_hour_1=0;set_minute_1=0;k_hour=0;k_minute=0;k_hour_1=0;k_minute_1=0;reset=0; if mode_in=1 then mode=1; if hour_in=1 then set_hour=1; k_hour=k; end if; if minute_in=1 then set_minute=1; k_minute=k; end if; if reset_in=1 then reset=1; end if; else mode=0; if hour_in_1=1 then set_hour_1=1; k_hour_1=k; end if; if minute_in_1=1 then set_minute_1=1; k_minute_1=k; end if; end if; end process; end fun;四、设计实现过程及测试结果记录；1 计时功能测试“ mode”为“1”时开始正常计时，当“set_hour”为“1”时，每次按动“k_hour”键一次，“小时”+1，若一秒内未按动“k_hour”键则小时以4Hz的频率递增计数，并按24小时循环，计满23小时后在回00；当“set_minute”为“1”时，每次按动“k_minute”键一次，“分钟”+1，若一秒内未按动“k_minute”键则分钟以4Hz的频率递增计数，并按60分钟循环，计满分钟后回00；按下“reset”键时，“小时”，“分钟”，“秒”清零；2 闹钟功能测试“ mode”为“0”时开始正常闹钟计时；当“set_hour_alarm每次按动“k_hour_alarm”键一次，“小时”+1，若一秒内未按动“k_hour_alarm”键则小时以4Hz的频率递增计数，并按24小时循环，计满23小时后在回00；当“set_minute_alarm”为“1”时，每次按动“k_minute_alarm”键一次，“分钟”+1，若一秒内未按动“k_minute_alarm”键则分钟以4Hz的频率递增计数，并按60分钟循环，计满分钟后回00；3 整点报时功能测试当计时到达5950时开始报时，在5951、53、55、57鸣叫，鸣叫频率可为512Hz；到达5959时发频率为1024Hz的高音，结束时为整点。4 闹钟报时功能测试当闹钟定时时间到时，蜂鸣器发出周期为1s的滴、滴声，持续时间为10s；5波形图：五心得体会； 六附设计文件明细表；序号文 件 名内 容 摘 要1计时模块Second.gdfMinute.gdfHour.gdfSecond.vhdMinute.vhdHour.vhdSecond.scfMinute.scfHour.scfSecond.sofMinute.sofHour.sof Reset为“1”：秒，分钟，小时清零K_minute为“1”：调整分钟，每按下set_minute一次，“分钟”+1； K_hour为“1”：调整小时，每按下set_hour一次，“小时”+1；序号文 件 名内 容 摘 要2闹钟