实验一 4位全加器的设计(1).doc

实验一 4位全加器的设计一、实验目的：1 熟悉Quartus与ModelSim的使用；2 学会使用文本输入方式和原理图输入方式进行工程设计；3 分别使用行为和结构化描述方法进行四位全加器的设计；4 理解RTL视图和Technology Map视图的区别；5 掌握简单的testbench文件的编写。二、实验原理：一个4位全加器可以由4个一位全加器构成，加法器间的进位可以串行方式实现，即将低位加法器的进位输出cout与相邻的高位加法器的进位输入信号cin相接。三、实验内容：1.QuartusII软件的熟悉熟悉Quartus环境下原理图的设计方法和流程，可参考课本第4章的内容，重点掌握层次化的设计方法。2.设计1位全加器原理图设计的原理图如下所示：VHDL源程序如下（行为描述）：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity f_add_bev isport (A: in std_logic;B: in std_logic;CIN: in std_logic;S: out std_logic;CO: out std_logic);end entity;architecture bev of f_add_bev isbegin(CO,S)=(0,A)+(0,B)+(0,CIN);end bev;VHDL源程序如下（行为描述）的RTL与technology map视图VHDL源程序如下（数据流描述）：library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity f_add_fl isport (A: in std_logic;B: in std_logic;CIN: in std_logic;S: OUT std_logic;CO: out std_logic);end entity;architecture fl of f_add_fl isbeginS=A XOR B XOR CIN;CO a,B = B,S = S1,CO = CO1);h_add2 : hadd_vhdport map (a = S1,B = CIN,S = S,CO = CO2);CO A , CO = CO , CIN = CIN , B = B , S = S ) ; A=NOT A AFTER 0.25US; B=NOT B AFTER 0.5US; CIN A0,B = B0,CIN = 0,S = S0,CO = CO0);f_add2 : fadd1_vhd port map (A = A1,B = B1,CIN = CO0,S = S1,CO = CO1);f_add3 : fadd1_vhd port map (A = A2,B = B2,CIN = CO1,S = S2,CO = CO2);f_add4 : fadd1_vhd port map (A = A3,B = B3,CIN = CO2,S = S3,CO = CO3);CO B0 , B1 = B1 , B2 = B2 , B3 = B3 , A0 = A0 , CO = CO , A1 = A1 , A2 = A2 , S0 = S0 , A3 = A3 , S1 = S1 , S2 = S2 , S3 = S3 ) ;A0 = not A0 after 0.1us; A1 = not A1 after 0.2us; A2 = not A2 after 0.4us; A3 = not A3 after 0.8us;B0 = not B0 after 0.2us; B1 = not B1 after 0.4us; B2 = not B2 after 0.8us; B3 = not B3 after 1.6us;END; 最终的功