基于Quartus2组件DSP_builder设计DDS信号发生器.docx

基于Quartus2组件DSP_builder设计DDS信号发生器说明：Quartus2中DSP_builder组件建立了Quartus2与Matlab的无缝链接，这样极大的有利于FPGA在信号处理中的应用，本次课题旨在通过建立一个信号发生器来说明DSP_builder的强大之处。传统的DDS信号发生器的设计相对比较复杂（包括相位累加器，地址查找表，D/A），通过传统的编程思想，会比较复杂，DSP_builder则是通过simulink中的Altera库，直接构建DDS模型，再通过signal complier生成VHDL语言以及仿真所用的测试脚本（testbench文件），非常方便，并通过simulink和FPGA的仿真工具Modelsim_Atera一起做了对比，两者吻合，达到了预期效果。 1.在Simulink中构建DDS模型 2.Simulink下的仿真如图所示：3.RTL级仿真（modelsim仿真）：4.RTL级视图附：.vhl代码- sinwafe_GN.vhdlibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;entity sinwafe_GN isport (Output : out std_logic_vector(7 downto 0); - Output.wireInput : in std_logic_vector(0 downto 0) := (others = 0); - Input.wireClock : in std_logic := 0; - Clock.clkaclr : in std_logic := 0 - .reset_n);end entity sinwafe_GN;architecture rtl of sinwafe_GN iscomponent alt_dspbuilder_clock_GNF343OQUJ isport (aclr : in std_logic := X; - resetaclr_n : in std_logic := X; - reset_naclr_out : out std_logic; - resetclock : in std_logic := X; - clkclock_out : out std_logic - clk);end component alt_dspbuilder_clock_GNF343OQUJ;component alt_dspbuilder_port_GNXAOKDYKC isport (input : in std_logic_vector(0 downto 0) := (others = X); - wireoutput : out std_logic_vector(0 downto 0) - wire);end component alt_dspbuilder_port_GNXAOKDYKC;component alt_dspbuilder_lut_GNV7OH7CRC isgeneric (use_lpm : natural := 0;reg_addr : natural := 0;reg_data : natural := 0;family : string := STRATIX;ADDRWIDTH : positive := 8;DATAWIDTH : positive := 8;RAMTYPE : string := AUTO);port (aclr : in std_logic := X; - clkclock : in std_logic := X; - clkena : in std_logic := X; - wireInput : in std_logic_vector(ADDRWIDTH-1 downto 0) := (others = X); - wireOutput : out std_logic_vector(DATAWIDTH-1 downto 0); - wiresclr : in std_logic := X - wire);end component alt_dspbuilder_lut_GNV7OH7CRC;component alt_dspbuilder_gnd_GN isport (output : out std_logic - wire);end component alt_dspbuilder_gnd_GN;component alt_dspbuilder_vcc_GN isport (output : out std_logic - wire);end component alt_dspbuilder_vcc_GN;component alt_dspbuilder_product_GNSX3UCWXH isgeneric (pipeline : natural := 0;UseDedicatedMult : natural := 0;lpm : natural := 0;MaskValue : string := 1;Signed : natural := 0;width : natural := 8);port (aclr : in std_logic := X; - clkclock : in std_logic := X; - clkdataa : in std_logic_vector(width-1 downto 0) := (others = X); - wiredatab : in std_logic_vector(width-1 downto 0) := (others = X); - wireena : in std_logic := X; - wireresult : out std_logic_vector(width*2-1 downto 0); - wireuser_aclr : in std_logic := X - wire);end component alt_dspbuilder_product_GNSX3UCWXH;component alt_dspbuilder_delay_GN53FGQEY3 isgeneric (width : positive := 8;delay : positive := 1;ClockPhase : string := 1;use_init : natural := 0;BitPattern : string := 00000001);port (aclr : in std_logic := X; - clkclock : in std_logic := X; - clkena : in std_logic := X; - wireinput : in std_logic_vector(width-1 downto 0) := (others = X); - wireoutput : out std_logic_vector(width-1 downto 0); - wiresclr : in std_logic := X - wire);end component alt_dspbuilder_delay_GN53FGQEY3;component alt_dspbuilder_inc_dec_GNM4UTC62W isgeneric (lpm : natural := 0;MaskValue : string := 1;direction : natural := 0;Unsigned : natural := 0;StartValue : string := 00000000;OutputWidth : integer := 8);port (aclr : in std_logic := X; - clkclock : in std_logic := X; - clkena : in std_logic := X; - wireresult : out std_logic_vector(OutputWidth-1 downto 0); - wiresclr : in std_logic := X - wire);end component alt_dspbuilder_inc_dec_GNM4UTC62W;component alt_dspbuilder_port_GNA5S4SQDN isport (input : in std_logic_vector(7 downto 0) := (others = X); - wireoutput : out std_logic_vector(7 downto 0) - wire);end component alt_dspbuilder_port_GNA5S4SQDN;component alt_dspbuilder_cast_GNQDULLOC6 isgeneric (saturate : natural := 0;round : natural := 0);port (input : in std_logic_vector(0 downto 0) := (others = X); - wireoutput : out std_logic_vector(7 downto 0) - wire);end component alt_dspbuilder_cast_GNQDULLOC6;component alt_dspbuilder_cast_GNXB66IQUO isgeneric (saturate : natural := 0;round : natural := 0);port (input : in std_logic_vector(15 downto 0) := (others = X); - wireoutput : out std_logic_vector(7 downto 0) - wire);end component alt_dspbuilder_cast_GNXB66IQUO;component alt_dspbuilder_cast_GNA72OVCRC isgeneric (saturate : natural := 0;round : natural := 0);port (input : in std_logic_vector(5 downto 0) := (others = X); - wireoutput : out std_logic_vector(5 downto 0) - wire);end component alt_dspbuilder_cast_GNA72OVCRC;signal sin_lutsclrgnd_output_wire : std_logic; - Sin_LUTsclrGND:output - Sin_LUT:sclrsignal sin_lutenavcc_output_wire : std_logic; - Sin_LUTenaVCC:output - Sin_LUT:enasignal productuser_aclrgnd_output_wire : std_logic; - Productuser_aclrGND:output - Product:user_aclrsignal productenavcc_output_wire : std_logic; - ProductenaVCC:output - Product:enasignal delaysclrgnd_output_wire : std_logic; - DelaysclrGND:output - Delay:sclrsignal delayenavcc_output_wire : std_logic; - DelayenaVCC:output - Delay:enasignal inccountsclrgnd_output_wire : std_logic; - IncCountsclrGND:output - IncCount:sclrsignal inccountenavcc_output_wire : std_logic; - IncCountenaVCC:output - IncCount:enasignal delay_output_wire : std_logic_vector(7 downto 0); - Delay:output - Product:dataasignal sin_lut_output_wire : std_logic_vector(7 downto 0); - Sin_LUT:Output - Delay:inputsignal input_0_output_wire : std_logic_vector(0 downto 0); - Input_0:output - cast0:inputsignal cast0_output_wire : std_logic_vector(7 downto 0); - cast0:output - Product:databsignal product_result_wire : std_logic_vector(15 downto 0); - Product:result - cast1:inputsignal cast1_output_wire : std_logic_vector(7 downto 0); - cast1:output - Output_0:inputsignal inccount_result_wire : std_logic_vector(5 downto 0); - IncCount:result - cast2:inputsignal cast2_output_wire : std_logic_vector(5 downto 0); - cast2:output - Sin_LUT:Inputsignal clock_0_clock_output_reset : std_logic; - Clock_0:aclr_out - Delay:aclr, IncCount:aclr, Product:aclr, Sin_LUT:aclrsignal clock_0_clock_output_clk : std_logic; - Clock_0:clock_out - Delay:clock, IncCount:clock, Product:clock, Sin_LUT:clockbeginclock_0 : component alt_dspbuilder_clock_GNF343OQUJport map (clock_out = clock_0_clock_output_clk, - clock_output.clkaclr_out = clock_0_clock_output_reset, - .resetclock = Clock, - clock.clkaclr_n = aclr - .reset_n);input_0 : component alt_dspbuilder_port_GNXAOKDYKCport map (input = Input, - input.wireoutput = input_0_output_wire - output.wire);sin_lut : component alt_dspbuilder_lut_GNV7OH7CRCgeneric map (use_lpm = 1,reg_addr = 1,reg_data = 0,family = Cyclone II,ADDRWIDTH = 6,DATAWIDTH = 8,RAMTYPE = AUTO)port map (clock = clock_0_clock_output_clk, - clock_aclr.clkaclr = clock_0_clock_output_reset, - .resetInput = cast2_output_wire, - Input.wireOutput = sin_lut_output_wire, - Output.wiresclr = sin_lutsclrgnd_output_wire, - sclr.wireena = sin_lutenavcc_output_wire - ena.wire);sin_lutsclrgnd : component alt_dspbuilder_gnd_GNport map (output = sin_lutsclrgnd_output_wire - output.wire);sin_lutenavcc : component alt_dspbuilder_vcc_GNport map (output = sin_lutenavcc_output_wire - output.wire);product : component alt_dspbuilder_product_GNSX3UCWXHgeneric map (pipeline = 0,UseDedicatedMult = 0,lpm = 0,MaskValue = 1,Signed = 1,width = 8)port map (clock = clock_0_clock_output_clk, - clock_aclr.clkaclr = clock_0_clock_output_reset, - .resetdataa = delay_output_wire, - dataa.wiredatab = cast0_output_wire, - datab.wireresult = product_result_wire, - result.wireuser_aclr = productuser_aclrgnd_output_wire, - user_aclr.wireena = productenavcc_output_wire - ena.wire);productuser_aclrgnd : component alt_dspbuilder_gnd_GNport map (output = productuser_aclrgnd_output_wire - output.wire);productenavcc : component alt_dspbuilder_vcc_GNport map (output = productenavcc_output_wire - output.wire);delay : component alt_dspbuilder_delay_GN53FGQEY3generic map (width = 8,delay = 1,ClockPhase = 1,use_init = 0,BitPattern = 00000001)port map (input = sin_lut_output_wire, - input.wireclock = clock_0_clock_output_clk, - clock_aclr.clkaclr = clock_0_clock_output_reset, - .resetoutput = delay_output_wire, - output.wiresclr = delaysclrgnd_output_wire, - sclr.wireena = delayenavcc_output_wire - ena.wire);delaysclrgnd : component alt_dspbuilder_gnd_GNport map (output = delaysclrgnd_output_wire - output.wire);delayenavcc : component alt_dspbuilder_vcc_GNport map (output = delayenavcc_output_wire - output.wire);inccount : component alt_dspbuilder_inc_dec_GNM4UTC62Wgeneric map (lpm = 0,MaskValue = 1,direction = 0,Unsigned = 0,StartValue = 000000,OutputWidth = 6)port map (clock = clock_0_clock_output_clk, - clock_aclr.clkaclr = clock_0_clock_output_reset, - .resetresult = inccount_result_wire, - result.wiresclr = inccountsclrgnd_output_wire,