频率测试仪2.doc

测频模块LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY cplj ISPORT( clk: INSTD_LOGIC; LOAD:out std_logic; CLR_CNT: OUTSTD_LOGIC; TSTEN: OUTSTD_LOGIC);END cplj;ARCHITECTURE a OF cplj ISSIGNAL Div2clk : STD_LOGIC;BEGINprocess(CLK) begin IF CLKevent and CLK=1 THEN Div2clk=not Div2clk; END IF; END process; process(CLK,Div2clk) BEGINIF CLK=0 and Div2clk=0 THEN CLR_CNT=1;ELSE CLR_CNT=0;END IF; END PROCESS ;LOAD=not Div2clk;TSTEN=Div2clk; END a; 计数器模块library ieee;use ieee.std_logic_1164.all;entity cnt10 isport(clk:in std_logic; clr:in std_logic; en:in std_logic; cq:out integer range 0 to 15; rco:out std_logic);end cnt10;architecture art of cnt10 is signal cqi:integer range 0 to 15; begin process(clk,clr,en) begin if clr=1then cqi=0; elsif clkevent and clk=1then if en=1 then if cqi9 then cqi=cqi+1; else cqi=0; end if; end if; end if;end process;process(cqi)begin if (cqi=9)then rco=1; else rco=0; end if;cq=cqi;end process;end art;寄存器模块library ieee;use ieee.std_logic_1164.all;entity reg32b is port(load:in std_logic; LED1,LED2,LED3,LED4,LED5 :in std_logic_vector(3 downto 0); dout1,dout2,dout3,dout4,dout5:out std_logic_vector(3 downto 0);end;architecture one of reg32b isbegin process(load) begin if loadevent and load=1 then dout1=LED1; dout2=LED2; dout3=LED3; dout4=LED4; dout5=LED5; end if; end process;end;七段译码显示模块LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY view ISPORT(in_data: INSTD_LOGIC_vector(3 downto 0); out_data: OUTSTD_LOGIC_vector(0 to 7);END view;ARCHITECTURE outview OF view ISSIGNAL indata : STD_LOGIC_vector(3 downto 0);BEGIN process(in_data) begin indataout_dataout_dataout_dataout_dataout_dataout_dataout_dataout_dataout_dataout_dataout_datastatestatestatestatestateiq=LED5;sel0=0;sel1=0;sel2iq=LED4;sel0=0;sel1=1;sel2iq=LED3;sel0=1;sel1=0;sel2iq=LED2;sel0=1;sel1=1;sel2iq=LED1;sel0=0;sel1=0;sel2=1;end case;end process p3;outdatastatestatestatestatestateiq=LED5;sel0=0;sel1=0;sel2iq=LED4;sel0=0;sel1=1;sel2iq=LED3;sel0=1;sel1