基于EDA技术的HDB3编码器的设计与实现.docx

Design based on HDB3 encoder of EDA technology and realizing Summary HDB3 yard is one of the important components in digital baseband communication system, because it does not have direct-flow compositions, it is strong to examine the ability by mistake, have advantages such as performance of clock recovery, etc, recommend the baseband that uses to transmit one of the yard types as ITU. Have introduced principle and method of HDB3 code at first, has proposed a method based on HDB3 encoder of EDA technology, have simple, with low costs circuit, development period is short, it is high to carry out the speed, upgrade characteristics such as convenience, etc. Foreword Third-order high-density bipolar code is an important serial data transmission encoding, digital communication is an important part of the system. And the most common NRZ code, compared, HDB3 code has many advantages, such as: eliminating the DC component NRZ code with clock recovery and better anti-jamming performance, making it more suitable for long-distance channel transmission. At the same time, HDB3 error detection code has a strong ability to use HDB3 code when the data transfer sequence, if a single bit error occurs during transmission, the law of alternating polarity will be destroyed, so the receiver HDB3 code based on the unique law characteristics, can be detected the error and correct the error, and facilitate the extraction of HDB3 code bit timing information. HDB3 code as data transmission and thus a pattern, widely used, as ITU recommended pattern one. HDB3 coding performed by the realization of a variety of ways, the common solution is application-specific transceiver chip HDB3, such as the selection of specific E1 transceiver and MCU DS2153Q the conversion of the code system. This article provides a the use of modern EDA technology to ACEX series FPGA chip EPlK10 for the hardware platform for the Quartus II software platform to VHDL, for the development of tools for FPGA implementation of the HDB3 encoder design. HDB3 yard High Density Bip01ar Code of three codes, a pair of polarity yard of high density for three steps It is an important code way of serial data transmission, it is one of the important components in the digital communication system too. And most frequently used NRZ yard Non-Return Zero, does not return zero yard Compare, HDB3 yard has a lot of advantages, for example: Dispel NRZ direct-flow composition of yard, have clock recovery and better interference-free performance, this makes it suitable for the channel of long distance to transmit. Meanwhile, HDB3 yard has more strongly examining the ability by mistake, when the data array is transmitted with HDB3 yard, if present yard singly by mistake in the transmission course, its polarity will change the law alternatively and will be destroyed, therefore is receiving the end according to one yard of this unique law characteristics of HDB3, can examine and make mistakes and correct the mistake, one yard of convenience of HDB3 drew the regular information in the location at the same time. Therefore one yard of a kind of code types as data transmission of HDB3, it is extensive to employ, become one of the yard types that ITU recommends using. There are multiple channels in the realization of HDB3 one yard of compiled code devices, commonly used solutions are to employ specialized HDB3 to receive and dispatch the chip, specialized E1 receives and dispatches chip DS2153Q and one-chip computer and realizes this yard of conversion function made such as selecting for use. This text offers one kind to utilize modern EDA technology, regard ACEX series FPGA chip EPlK10 as the hardware platform, regard Quartus II as the software platform, with VHDL, it is a developing instrument, the design plan of HDB3 encoder that suitable FPGA realizes. 1 Code rule of HDB3 yard The code rule of HDB3 yard is as follows: (1)Vary the news code into AMI yard; AMI yard Alternate Mark Inversion Full name to spread number, overturn yard alternatively. This one kind encodes code 0 and 1 of news according to the following rule: Last yard 0 code 0 still, and at code if you can?t turn into, transmit alternative by that yard to 1 ,1, -1, 1, -l; (2)Check the intersection of AMI and connecting 0 situation with in the yard, as 4 or more of having connect 0 bunches with, keep the form of AMI not changing; Appear 4 or more connect 0 with, 0 turn 4th after the 1 into until the first one the intersection of O and yard With the symbol of polarity, show n is own is V, it is V n is own with V; (3)Check whether not 0 yards of numbers among adjacent v yard is an even number, if is the even number, again present V yard the first one the first 0 yard later turn by B yard B into for 0 times, and is a the first one is the polarities of yard opposite of O the polarities of B, and make not 0 yards behind begin to replace the change from V yard. NRZ one yard of course changed into HDB3 yard such as Table 1 shown for example. 2 Modeling and realizing of HDB3 encoder Go on data that encode according to encode the principle to convert to AMI yard first while being above-mentioned directly, then go on, add the intersection of V and yard, add the intersection of B and yard, operate, will find, transform the intersection of AMI and yards of one the 1 occasionally into one 1 Yards of course that polarity form, but after adding B yard and operating, only if zero yuans of corresponding polarity might overturn, so there are two pieces of course that signal polarity produces. Analyze the code result of HDB3: V positive to shoulder not alternative in polarity of yard, remaining 1 and the intersection of B and yard regard as until an organic whole positive to shoulder not alternative too, meet the intersection of V and polarity with the intersection of zero and identical polarity of in the front of yard at the same time. Therefore has produced the thinking that use FPGA carries on HDB3 one yard of codes: Go on and add V yard first, adds B yard and operates, in this course, wouldnt consider its polarity, then the intersection of V and yard, 1 divide two into with the intersection of B and yard, carry on polar variety come on one realize respectively. So it can raise the efficiency of the system, the decrease system delays time at the same time. The digital circuit part of HDB3 encoder is made up of three pieces of module: V yard produced the unit V Gen ,B yard produced the unit B Gen ,A pair of polar conversion units single2double of single polarity ,Their structure charts. 2. 1 V yard produced the unit V_Gen V one yard of functions of producing the unit is to connect four in the news code with 0 bunches of detection in fact, namely when connecting with 0 bunches four, vary, succeed V yard fourth 0, but otherwise, keep the former state of the news code exporting. For offer the convenience to encoding the course, transmit yard, say with 2 binary scale one the intersection of code and yuan in the original signal, while going on with V yard, use?11? in unison Annotate it, original l yard uses 01Annotate, 0 yards use 00Annotate. Fig. 2 shows for V one yard of job flow diagrams which produces the unit. The original signal NRZ_in produced the unit V_Gen through V yard And then signal V_Gen_out wave form: 2. 2 B yard produced the unit B_Gen B one yard of functions of producing the unit is to guarantee the additional V array after yard is not destroyed ?Polarity overturns alternatively Direct-flow characteristic does not formed, namely when there are a piece of not 0 yards of even number between adjacent V yard, after one is small for that section if you cant vary as, destroy by symbol a B of yards 4 each to the first times 0. So, while judging whether some one 0 should be turned into B, should guarantee at first thereafter code yuan of third are one yard of yuan of V, so must until each go on, store temporarily at present, it waits for to be thereafter third the intersection of code and arrival of yuan. For realize purpose this, at first each insert V punish Put into the displacement register of 3 for one, under the function of the synchronous clock, whether add the judgment of B yard at the same time, when yard of yuan are from shifting to come out in the register, can determine to vary into B yard, shine the original yard of outputs. Fig. 4 shows for B one yard of job flow diagrams which produces the unit. The signal V_Gen_out produced the unit B_Gen through B yard after adding V And then signal B_Gen_out wave form. 2. 3 form polarity one pair of polar conversion units single 2 double According to the code rule of HDB3, we can know, the polarity of V yard is positive defeated by the alternative one, remaining 1 and the intersection of B and yard regard as until an organic whole and positive to shoulder not alternative, meet the intersection of V and polarity with the intersection of zero and identical polarity of in the front of yard at the same time. Therefore we can carry on separately polar variety of it to realize. Know from the procedure of the front, V, B, 1Have already used one pair of phases yard separately 11, 10, 01 Annotate it, 0Use 00 Annotate, so we can realize very easily through the following procedures. Fig. 5 shows for the job flow diagrams of a pair of polar conversion units of single polarity. Through a pair of polar transformation units of single polarity, 1 including 1, V, B Use 2 binary scale yard 01 Show 1 the 1 the V the BUse 2 binary scale yard 11 Show, 0 use 2 the intersection of binary scale and yards of the 00 Show, the advantage encoded like this is, when we regard two high positions of yard of binary scale that the code transform into as having sign bit that the symbol counts, 01, 11 , 00 Correspond to 1, 1, 0 separately. Help us observe the artificial result like this. The signal B_Gen_out passes a pair of polar conversion units single2double of single polarity after adding B And then signal Code out wave form. Single 3 / pairs of polar hardware circuit of variety Download the above-mentioned procedure to the programming device, the code result produced is one pair of level signals of single polarity. This signal is not real HDB3 yard yet, need to be above-mentioned to encode to convert to 1 the 1 , 0 Level changes the wave form, but work to depend on the digital circuit cant be finished simply here. The directness way of comparison, utilize the code result, control many way simulation selector switches to realize, 4 selects a simulation selector switch CD4052 of the way such as utilizing pair, their 5 tables of function are shown in Table 2. Utilize many ways to imitate the selector switch CD4052 and realize the circuit connection diagram that level changed, HDB3_out is that standard HDB3 yard formed finally flows in the picture. 3 conclusionsEDA is a kind of industrial production technology, use the programmable chip based on that the hardware describes the language and can describe the hardware to the relevant circuit in the communication system while developing technology in practice, then realize the digital communication system with CPLD/ FPGA and combine the design cycle that electronic design automation and artificial technology of the circuit can narrow the products at the same time, reduce the mistake that may happen, improve development benefit of the communication products. Practice show, use FPGA come, realize the intersection of NRZ and yard to the intersection of HDB3 and conversion of yard than adopt the specialized integrated circuit debug and bring convenience, defect of overcoming the interference-free difference that the circuit of the discrete hardware brings and difficult to adjust etc., it is short, with low costs and have software development period, it is high to carry out the speed, the real-time character is strong, upgrade characteristics such as convenience, etc. And can integrate this circuit and its decoding circuit and other functions circuit in the same FPGA chip, having reduced the number of connecting the component, has improved the integrated level, and there is very great programming flexibility, very strong transplantation, so there is very good application prospect. 基于EDA技术的HDB3编码器的设计与实现 摘要 HDB3码是数字基带通信系统的重要组成部分之一，因为它没有直流组成功能强大有纠错能力具有时钟恢复等性能优势,是ITU建议使用的基带类传输码型之一。本文首先介绍了HDB3码的原理提出了基于EDA技术的HDB3编码器的实现方法,其具有电路简单、成本低、开发周期短、执行速度快、升级方便等特点。 前言 HDB3码(三阶高密度双极性码是串行数据传输的一种重要编码方式，也是数字通信系统中重要组成部分之一。和最常用的NRZ码(非归零码)相比，HDB3码具有很多优点，例如：消除了NRZ码的直流成分，具有时钟恢复和更好的抗干扰性能，这使它更适合于长距离信道传输。同时HDB3码具有较强的检错能力，当数据序列用HDB3码传输时，若传输过程中出现单个误码其极性交替变化规律将受到破坏，因而在接收端根据HDB3码这一独特规律特性，可检出错误并纠正错误，同时HDB3码方便提取位定时信息。因而HDB3码作为数据传输的一种码型应用广泛成为ITU推荐使用的码型之一。HDB3码编译码器的实现有多种途径，常用的解决方案是应用专用的HDB3收发芯片如选用专用E1收发芯片DS2153Q和单片机实现该码制的转换功能。本文提供了一种利用现代EDA技术以ACEX系列FPGA芯片EPlK10为硬件平台，以Quartus II为软件平台以VHDL 为开发工具，适合于FPGA实现的HDB3编码器的设计方案。 高密度的HDB3码的编码守则也称为3连零守则，一条有极性的高密度信息码分为三个步骤编成。这是一种重要的代码串行数据传输方式也是在数字通信系统中的重要组成部分之一。和最常用的非归零的NRZ码和不归零码比较采用HDB3码具有很多优点，例如：消除了 NRZ码的直接流部分组成，有更好的时钟恢复和抗干扰的性能，这使得它更适合在长途传输通道中传输。同时HDB3码有更强大的误码检测能力，当传输的数据阵列为HDB3码时，如果当前的码单通过在传输过程中出错，其极性交替规律将会被改变或被破坏，因此在接收端凭借着HDB3码独特的性质，就可以检查错误和改正错误并同时在相应的位置上提取出正确的信息。因此HDB3码成为了ITU建议使用的一种数据传输码型，被广泛的应用于各个领域。现在，我们拥有基于不同方式来实现HDB3码编译的设备，常用的解决方案是采用专门的HDB3收发芯片，选择使用专用的E1收发芯片DS2153Q和单芯片计算机作为实现这种转换功能码的设备。这篇研究报告提供了一种利用现代EDA技术，它是一种开发的工具把ACEX系列FPGA芯片作为硬件平台EPlK10。以Quartus II软件为平台，使用VHDL 在设计HDB3编码器的方案时由FPGA予以实现。 1 HDB3码的编码规则 HDB3码的编码规则如下 1先将一条信息码元变化成AMI码 AMI码的全称是传号交替反转码是通信编码中的一种为极性交替翻转码分别有一个高电平和低电平表示两个极性。消息代码中的0在传输码中仍用0消息代码中的1在传输码中用+1和-1交替代换。 2检查AMI代码中的连0情况 如果出现4个以下连0的情况则保持AMI码的形式不变如果为4个或更多的连0时，从1后开始每4个0编为1小节每小节的第四个0变为与前一个1极性相反的V+V和-V是交替出现的。 3检查是否不为0的码中相邻V码的个数为偶数 如果为偶数将第一小节的第一个0变成与节前1极性相反的B后面的小节中第一个0则变为与前小节中B极性不同的B而每小节中V的极性与B相同。 2 HDB3编码器的建模与实现如果直接将要进行编码的数据按上述编码原则先转换成AMI码，然后进行加V码，加B码操作，会发现转化成AMI码时有一个“+1”、“-1”码极性形成的过程，而在加B码操作之后，非零码元相应极性还有可能进行反转，因此有两个信号极性产生的过程。 分析HDB3的编码结果V码的极性是正负交替的，余