VHDL电子时钟的设计.doc

现代电子系统设计中北学院现代电子系统设计_数字电子钟实验报告姓名:叶子班级:0932班学号:专业:电子信息工程任课教师:倪小琦完成时间:2012年5月19日2518093203叶子目录第一章数字电子钟功能简介3第二章数字电子钟原理介绍32.1数字电子钟基本原理 32.2数字电子钟电路组成 3第三章利用QuartusII设计数字电子钟 73.1按键去抖动模块 73.2分频电路模块 93.3选择器模块133.4计数模块143.5分位电路模块183.6数码管动态显示扫描模块213.7数码管动态显示模块22第四章仿真与实现25第一章数字电子钟功能简介 计时功能：这是本计时器设计的基本功能，可进行时、分、秒计时，并显示在6个七段数码管上。 调时功能：当需要校时，可通过实验箱上的按键控制，按下对应的按键，可调整对应的时、分状态。第二章数字电子钟原理简介2.1数字电子钟基本原理 数字钟电路的基本结构由两个60进制计数器和一个24进制计数器组成，分别对秒、分、小时进行计时，当计时到23时59分59秒时，再来一个计数脉冲，计数器清零，重新开始计时。秒计数器的计数时钟CLK为1Hz的标准信号，可以由27MHz信号通过分频得到。当数字钟处于计时状态时，秒计数器的进位输出信号作为分钟计数器的计数信号，分钟计数器的进位输出信号又作为小时计数器的计数信号。时、分、秒的计时结果通过6个数码管来动态显示。数字钟除了能够正常计时外，还应能够对时间进行调整。可通过模式选择信号控制数字钟的工作状态，即控制数字钟，使其分别工作于正常计时，调整分、时和设定分、时状态。当数字钟处于计时状态时，3个计数器允许计数，且秒、分、时计数器的计数时钟信号分别为CLK，秒的进位, 分的进位；当数字钟处于调整时间状态时，被调的分或时会一秒一秒地增加。2.2数字电子钟电路组成 本实验数字电子钟的设计电路主要由七个模块组成，分别是：按键去抖动模块、分频电路模块、选择器模块、计数模块、分位电路模块、数码管动态显示扫描模块、数码管动态显示模块。按键去抖动模块如图2-1所示 图2-1分频电路模块如图2-2所示图2-2选择器模块如图2-3所示图2-3计数模块如图2-4所示图2-4分位电路模块如图2-5所示图2-5数码管动态显示扫描模块如图2-6所示图2-6数码管动态显示模块如图2-7所示图2-7电路图整体设计如图2-8所示图2-8第三章利用QuartusII设计数字电子钟3.1按键去抖动模块按键去抖动模块的元件设计如图3-1所示图3-1按键去抖动的VHDL语言设计如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity debounce isport(clk:in std_logic;qcin:in std_logic;qcout:out std_logic);end debounce;architecture behave of bounce istype state is (S0,S1,S2);signal current: state;Beginprocess(clk,qin)begin if(clkevent and clk = 1) thencase current iswhen S0 = qcout = 1;if(qcin = 0) thencurrent = S1;elsecurrent qcout = 1;if(qcin = 0) thencurrent = S2;elsecurrent qcout = 0;if(qcin = 0) thencurrent = S2;elsecurrent qcout = 1;current = S0;end case;end if;end process;end behave;/3.2分频电路模块分频电路模块元件设计如图3-2所示：图3-2分频模块VHDL语言设计如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity clk1kHz isgeneric(N: integer:=50000); port(clk: in std_logic;clk1kHz: out std_logic);end clk1kHz;architecture behave of clk1kHz issignal cnt: integer range 0 to N/2-1; signal temp: std_logic;Begin process(clk) begin if(clkevent and clk=1) then if(cnt=N/2-1) then cnt = 0; temp = NOT temp; else cnt = cnt+1; end if; end if; end process; clk1KHz = temp;end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity clk1Hz isgeneric(N: integer:=50000000); port(clk: in std_logic;clk1Hz: out std_logic);end clk1Hz;architecture behave of clk1Hz is signal cnt: integer range 0 to N/2-1; signal temp: std_logic;Begin process(clk) begin if(clkevent and clk=1) then if(cnt=N/2-1) then cnt = 0; temp = NOT temp; else cnt = cnt+1; end if; end if; end process; clk1Hz = temp;end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity clk10Hz isgeneric(N: integer:=20000000); port(clk: in std_logic;clk10Hz: out std_logic);end clk10Hz;architecture behave of clk10Hz issignal cnt: integer range 0 to N/2-1; signal temp: std_logic;Begin process(clk) begin if(clkevent and clk=1) then if(cnt=N/2-1) then cnt = 0; temp = NOT temp; else cnt = cnt+1; end if; end if; end process; clk10Hz = temp;end behave;/3.3选择器模块选择器模块元件设计如图3-3所示：图3-3选择器模块VHDL与颜色合计如下所示：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xzq isport(sel: in std_logic;date0,date1:in std_logic;dcout:out std_logic);end xzq;architecture behave of xzqisbeginwith sel selectdcout =date0 when 0, date1 when others;end behave;/3.4计数模块计数模块元件设计如图3-4所示：图3-4计数器模块VHDL语言设计如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count60s isport(clk:in std_logic;clk10:in std_logic;set: in std_logic:=1;change: out std_logic;qcout: buffer integer range 0 to 59:=0);end count60s;architecture behave of count60s issignal temp:integer range 0 to 59;signal temp1:std_logic; begin process(clk,set,clk10) begin if(set=0) thentemp = 0; elsif(clkevent and clk=1) then if(qcout=59) thentemp = 0;temp1 = 1; elsetemp = temp+1;temp1 = 0; end if; end if; qcout = temp; change = temp1; end process; end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count60m isport(clk:in std_logic;change: out std_logic;qcout: buffer integer range 0 to 59:=0;set:in std_logic:=1);end count60m;architecture behave of count60m issignal temp:integer range 0 to 59;signal temp1:std_logic; begin process(clk) begin if(clkevent and clk=1) then if(qcout=59) thentemp = 0;temp1 = 1; elsetemp = temp+1;temp1 = 0; end if; end if; qcout = temp; if(set = 1)thenchange = car;end if; end process; end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count24h isport(clk:in std_logic;qcout: buffer integer range 0 to 23:=0);end count24h;architecture behave of count24h issignal temp:integer range 0 to 23; begin process(clk) begin if(clkevent and clk=1)then if(qcout=23) thentemp = 0; elsetemp = temp+1; end if; end if; qcout = temp; end process; end behave;/3.5分位电路模块分位电路模块元件设计如图3-5所示图3-5分位电路模块VHDL语言设计如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity decircuit isport(cnt: in integer range 0 to 59;ge: out integer range 0 to 9;shi: out integer range 0 to 9);end decircuit;architecture behave of decircuit isbegin-fenwei circuitprocess(cnt)variable shi_temp:integer;beginge = cnt mod 10;shi = cnt / 10;end process;end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity decircuit isport(cnt: in integer range 0 to 59;ge: out integer range 0 to 9;shi: out integer range 0 to 9);end decircuit;architecture behave of decircuit isbeginprocess(cnt)variable shi_temp:integer;beginge = cnt mod 10;shi = cnt / 10;end process;end behave;/library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity decircuit2 isport(cnt: in integer range 0 to 23;ge: out integer range 0 to 9;shi: out integer range 0 to 9);end decircuit2;architecture behave of decircuit2 isbegin-fenwei circuitprocess(cnt)variable shi_temp:integer;beginge = cnt mod 10;shi = cnt / 10;end process;end behave;/3.6数码管动态显示扫描模块图3-6元件设计如图3-6所示：图3-6数码管动态显示扫描模块VHDL语言设计如下：library ieee;use ieee.std_logic_1164.al