SC8211规格书.doc

SC8211 16 Bit Digital to Analog ConverterDESCRIPTIONSC8211 is a dual channel, 16 bit digital -to-analog converter IC utilizing CMOS technology specially designed for the digital audio applications. The internal conversion architecture is based on a R-2R resister ladder network, internal circuit is well matched and a 16 bit dynamic range is achieved even in whole supply voltage range. SC8211 also enhanced the performance of timing responsibility in digital serial bus, in a company with the fast switching R-2R network that make 8X over sampling audio signal is also supported.SC8211 can be supported wide range of sample frequency, it is compatible with TDA1311 by functionally. Its digital input timing format is Least Significant Bit Justified (LSBJ), or so called Japanese input format. Digital code format is twos complement and MSB first. SC8211 is available in 8-pin SOP or DIP. FEATURES CMOS technology Support 3.3V bus input level Low power consumption Two audio channel output in the same chip 16 bit dynamic range Low total harmonic distortion No phase shift between both output channel Available in 8 pins, SOP or DIPAPPLICATIONS Digital audio equipment CD ROM/VCD Multimedia sound card MPEG decoder cardBLOCK DIAGRAMPIN CONFIGURATIONPIN DESCRIPTIONPin NameI/ODescriptionPin No.BCKISerial bit clock input1WSIWord select clock input pin2DINIData input pin3GND-Ground4VDDPowerPositive power supply5LCHOLeft channel output6NC-No connection7RCHORight channel output8FUNCTION DESCRIPTIONThe serial bus input data format of SC8211 is Japanese or called LSBJ (Least significant bit justified) format. Each valid DIN data will be shifted to the input register in the rising edge of the BCK, only the first 16 bit data (from MSB) is valid if the input data length is more than 16 bit, other data bit will be truncated. The clock frequency of the BCK could run up to 20MHz and supported to 8X over-sampling in 48KHz WS clock rate. Both left and right data words are time multiplexed. Please refer to the diagrams for timing and input signal formats.Figure 2. Timing and Input Signal FormatsThe DIN data must be the 2s complementary format and the MSB (Most significant bit) must be the first. When the word select (WS) clock in the Low level, the DIN data will be shifted to the right input register. Likewise, the DIN data will be shifted to the left input register when WS clock in the high level. The buffered DIN data then feeding to the DAC after both input register are all settled down, this can eliminated the phase shift happened between two channel output. DAC output is generated by a 16 bit R-2R resistor ladder network. This signal is driven to the Right/ Left Channel (RCH/LCH) via the buffer operational amplifier.ABSOLUTE MAXIMUM RATINGSParameterSymbolRatingUnitPower supply voltageVDD-0.37.0VInput voltageVI-0.3VDD+0.3VOperating temperatureTopr-40+85Storage temperatureTstg-65+150DC CHARACTERISTICS(Test conditions: Ta = 25, VDD = 5.0V, unless otherwise specified)ParameterSymbolConditionMinTypMaxUnitPower supply voltageVDDTHD1%356VOperating currentISVDD=5V101318mADigital input high level*1VIH1.82.2VCCVDigital input low level*1VILGND1.21.8VNote: *1 digital input level will changed due to supply voltage.TIMING CHARACTERISTICS (Please to the figure 1)ParameterSymbolConditionMinTypMaxUnitBit clock frequencyFbckBCK-18.4MHzWord clock frequencyFwsWS-384KHzInput data rateFdinDIN-18.4Mbits/SH level timetH25nsRise timetR20nsFall timerF20nsANALOG AUDIO CHARACTERISTICS (Test condition: Ta = 25, VDD = 5.0V, unless otherwise specified)ParameterSymbolConditionMinTypMaxUnitMaximum output levelVOVPPTotal harmonic distortionTHD1KHz, 0dB Fs-0.130.3%1KHz, -10dB Fs0.080.10.21KHz, -60dB Fs-36MonotonicityMt-16BitDynamic rangeDR8589-dBSignal to noise ratioS/NData = 0000H8993-dBNo clock input-9597Cross talkCtaBoth outputChannel808992dBCTdDigital in toAnalog out7580-Phase shiftPdBoth outputchannel-00.2uSAPPLICATION CIRCUIT AND NOTETo further suppress residual noise, we suggest placing an additional low pass filter after the analog output of SC8211. Please refer to the circuit diagram below. This is a simple second-order analog post filter. If low noise output is very important for your circuit design we suggest using a regulated power supply.ORDERING INFORMATIONOrder part numberPackage typeTop codeSC8211-S8 Pins, SOP, 150milSC8211-SSC82118 Pins, DIP, 300milSC8211Notes:1. (L) = Lead Free2. The lead free mark is put in front of the date code.PACKAGE INFORMATION8 PINS, SOP, 1500MILSymbolMinNomMaxA1.351.75A10.100.25B0.330.51C0.190.25D4.805.00E3.804.00E1.27 bsc.H5.806.20H0.250.50L0.401.2708Notes:1. Dimensioning and tolerance per ANSI Y14.5M-1982.2. Dimension ”D” does not include mold flash, protrusions or gate burrs. Mold Flash, protrusion or gate burrs shall not exceed 0.15 mm (0.006 in) per side.3. Dimension “E” does not include interplead flash or protrusions. Interplead flash or protrusions shall not exceed 0.25 mm (0.010 in) per side.4. The chamfer on the body is optional. It is not present, a visual index feature must be located within the crosshatched area.5. “L” is the length of the terminal for soldering to a substrate.6. N is the number of the terminal positions (N = 8).7. The lead width “B” as measured 0.36 mm (0.014 in) or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.24 in).8. Controlling dimension: MILLIMETER.9. Refer to JEDEC MS-0.12, Variation AA.JEDEC is the trademark of JEDEC SOLID STATE TECHNOLLOGY ASSOCIATION.8PINS, DIP, 300MILSymbolMinNomMaxA-0.210A10.015-A20.1150.1300.195b0.0140.0180.022b10.0140.0180.020b20.0450.0600.070b30.0300.0390.045c0.0080.0100.014c10.0080.0100.011D0.3550.3650.400D10.005-E0.3000.3100.325E10.2400.2500.280e0.100 bsc.eA0.300 bsc.eB-0.430eC0.000-0.060L0.1150.1300.150Notes:1. Controlling dimensions: INCHES.2. Dimensioning and tolerance per ANSI Y14.5M-1982.3. Symbols are defined in the “MO Series Symbol LIST” in section 2.2 of publication No.95.4. Dimension A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.5. D, D1 and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch.6. E and eA measured with the leads constrai