GC0306_V2_DS中文翻译.doc

GC0306 1/6 CMOS VGA CAMERACHIP Preliminary Datasheet格科微电子有限公司1/6英寸CMOS摄像头芯片GC0306 概述 GC0306 是一种1/6英寸的数字COMS图像传感器。使用在 VGA (640X480)标准的摄像手机和PC摄像头中。基于 3.6um 像素的体系结构, GC0306 能够微型化为 6 x 6 x 3.7 mm (CSP 模块) 或者6.5 x 6.5 x 3.75 mm (COB 模块)。一个很小的GC0306 图像传感器设备支持 单芯片的VGA照相机和图像处理器的所有功能。所需的所有图像处理功能包括曝光控制，白平衡，去噪，边沿增强，颜色校正，伽吗调整，饱和度调整等等，都通过一个简单的I2C接口编程实现。以不同的形式（原始RGB,RGB(RGB565/RGB555/RGB444),YCbCr(4:2:2)）输出全帧,补充抽样或者窗口化的8位图像。通过格科的特殊处理, GC0306能为客户提供 低噪声，低功耗，高集成度，宽动态范围和优越的暗光性能。特征: 暗光下工作的高灵敏度High sensitivity for low-light operation 低工作电压便于嵌入便携式应用Low operating voltage for embedded portable applications. 标准的SCCB接口与I2C接口一致Standard SCCB interface compatible with I2C interface 输出支持原始RGB, RGB (RGB565/555/444), YCbCr (4:2:2)形式Output support for Raw RGB, RGB (RGB565/555/444), YCbCr (4:2:2) formats 窗口定位拍摄全景Window sizing and panning 支持补充取样Supports sub-sampling 自动白平衡控制Automatic white balance (AWB) control. 自动曝光控制Automatic expose control (AEC) 镜头阴影矫正Lens shading correction (LSC). 平面缺陷矫正2-D defect correction 良好的边缘保存去除噪声2-D noise removal with good edge preserving 通过各向边缘增强提高缺口插值Advanced bayer interpolation with isotropy edge enhancement. 边缘增强标准可编程性Edge enhancement level programmable. 鲜明的颜色矫正Vivid color correction 可编程的伽吗曲线矫正Programmable Gamma curve correction 可编程的对比度和饱和度调整Programmable contrast and saturation adjustment 支持任意颜色效果调整Optionally color effect tuning support 人的肤色探测和矫正Human skin detection and correction 支持LED和flash频闪模式Supports LED and flash strobe mode.分类信息产品封装GC0306-CCM2024Pin GC0306-PLCC28Pin产品规格参数值像素矩阵尺寸 640 x 480电源数字1.8V10%模拟2.8V10%I/O2.8V10%功率要求有效功率60 mW 典型最大电流20uA实物大小1/6” (对角线)像素尺寸3.6u x 3.6u有效入射角25最大图像转化率30fps for VGA 60fps for QVGA输出形式 (8-bit)s YCbCr 4:2:2s RGB565/555/444s Raw RGB data扫描形式渐进式电子编程阀门0 rows to 4095 rows图像面积2.36mm x 1.76 mm封装尺寸3446 um x 3794 mm图1 结构图图2 引脚图 (顶视图)表1 引脚描述引脚名称引脚类型描述A1AVDDPower2.8V 模拟电路电源.A2SBDABi-direction串口数据 I/O.A3SBCLInput串口时钟输入.A4D1Output输出数据 bit 1A5D3Output输出数据bit 3B1PWDNInput芯片调电标准0: 正常模式 1: 掉电模式B2VREF参考电压B3AGNDPower模拟地B4D0Output输出数据t bit 0B5D2Output输出数据bit 2C1DVDD18Power1.8V 数字电压C2DGND数字地D1VSYNCOutput输出垂直同步信号D2HSYNCOutput输出水平同步信号E1OPCLKOutput输出像素时钟E2STROBEOutput阀门控制输出E3IN_CLKInput外部时钟输入E4D7Output输出数据t bit 7E5D5Output输出数据bit 5F1DVDD33PowerI/O口数字电源F2RESET_BInput复位所寄存器到默认值.0: 复位模式 1: 正常模式F3DGNDPower数字地.F4D6Output输出数据 bit 6F5D4Output输出数据 bit 4电气参数 省略表2 Absolute Maximum RatingsAmbient Storage TemperatureSupply Voltages(with respect to Ground)VDD-AVDD-CVDD-IOAll input/output Voltages (with respect to Ground)Lead-free Temperature, Surface-mount processESD Rating, Human Body modelTable 3 DC Characteristics SymbolParameterConditionMinTypMaxUnitVDD-ADC supply voltage - AnalogVDD-CDC supply voltage Digital CoreVDD-IODC supply voltage I/O powerIDDAActive(Operating) CurrentIDDS-SCCBStandby CurrentIDDS-PWDNStandby CurrentVIHInput voltage HIGHVILInput voltage LOWVOHOutput voltage HIGHVOLOutput voltage LOWIOHOutput current HIGHIOLOutput current LOWILInput/Output LeakageFunction Block DescriptionSensor CoreFigure 3 Sensor Core DiagramFigure 3 Sensor Core DiagramThe sensor cores active pixel array is configured as 648 columns by 488 rows, which can avoid boundary affects during de-noise and color interpolation, and provide the VGA (640X480) image. The sensor core uses the RGB Bayer color pattern. The image data is read-out in a progressive scan. Image Signal ProcessorAs shown in Figure 4, the Image signal processor consists of a color processing pipeline and a measurement and control logic block. The color processing pipeline receives the source data from the sensor core and processes them by a number of transformations, include linear response correction, lens shading correction, 2-D defect correction, interpolation, edge enhancement, color correction, gamma correction, saturation and contrast correction, and output format setting. The camera control module accumulates statistics about image brightness and color which is provided by the color pipeline module, and gets suitable exposure time and white balance parameters and so on.Figure 4 ISP Block DiagramsSerial Communication Interface 1. Protocol Device Address: serial bus read address = 21H, serial bus write address = 20H.The host must perform the role of a communications master and GC0306 acts as either a slave receiver or transmitter. The master must do Generate the Start(S)/Stop(P) condition Provide the serial clock on SBCL.Figure5 Serial Communication State DiagramFigure 6 Register WritingS 20H A Index A Data1 A DataN A P Figure 7 Registers Reading S20HAIndexAS21HADataR1ADataRNNAPNote - S: Start P: Stop A: Acknowledge bit. (If there are still have read data, send back “A” )NA: Not-acknowledge bit. (If there are no more read data, send back “NA” ) 20H: Writing Address (8 bits) 21H: Reading Address (8 bits) Index: Register Address (8 bits) Data1, , DataN: Writing data (8 bits) DataR1, , DataRN: Reading Data2. Serial Bus TimingFigure 8 Serial Bus Timing Diagram Table 4 Serial Interface Timing ParametersParameterSymbolMin.Max.UnitSBCL clock frequencyfscl0400KHzBus free time between a stop and a starttbuf1.2*msHold time for a repeated startthd;sta1.0*msLOW period of SBCLtlow1.2*msHIGH period of SBCLthigh1.0*msSet-up time for a repeated starttsu;sta1.2*nsData hold timethd;dat1.3*nsData Set-up timetsu;dat250*nsRise time of SBCL, SBDAtr*250nsFall time of SBCL, SBDAtf*300nsSet-up time for a stoptsu;sto1.2*msCapacitive load of bus line (SBCL, SBDA)Cb*pfOutput Data Format1. Output Frame TimingFigure 9 Output Frame TimingIn GC0306, the polarities of VSYNC and HSYNC can be inversed. The figure 8 shows the condition in which VSYNC and HSYNC are high valid. There are two sync modes for video output interface: one with the edges of vertical frame sync and horizontal line sync indicated by output pin VSYNC and HSYNC, another with the Hsync_header information embedded in data bus D7:0. The Hsync_header can be skipped by register setting. If the Hsync_header is used, the first line of one frame image is marked by the sequence of 0xFF,0x00,0x00,0xF1, and following line is marked by the sequence of 0xFF,0x00,0x00,0xDA.Table 5. Frame Time with default setting: Parameter Name EQUATIONRtRow timeRt = 854 + Hb; Hb is defined by Reg0x01 （default =72）StFrame Start timeSt =(Vspos*8+9)*Rt ; Vspos is set by Reg0x0f 7:5EtFrame End timeEt = (489+Vb-Vt-St)* Rt VwVSYNC High TimeVw = St+(Output Image Height)*Rt +Et; FtTotal Frame timeIf Exposure time 490+VbFt=(490+Reg0x02)*RtElse Ft=(Reg0x03*256+Reg0x04+1)*Rt2. Out Pixel TimingFigure 10 Out Pixel TimingTable 6 : Out Pixel Timing Parameters:ParameterDescriptionMinTypMaxUnittpdvOPCLKs negtive edge to data-out valid5nstsuD7:0 setput time15nsthdD7:0 hold time8nstphhOPCLKs edge to HSYNCs edge5nsFigure 11 YCbCr 4:2:2 output timingFigure 12 RGB565 output timingRegister List:Addr(Hex)RegisterNameWidthDefault(Hex)R/WDescription00PID8D1RProduct ID01HB848RWHorizontal blank pixel numberTotal blank = (184+Hb) pixel clks02VB822RWFrame rate control1 Row to 255 Rows03EXPH43RWThe high 4 bit of expose time.Expose time = EXPH*256+EXPL04EXPL80RWThe low 8 bit of expose time.05RSTH10RWRow starting High byteRowstart= RSTH*256+RSTLRange: 0(489-WindHeight)06RSTL80RWThe low 8 bit of row start position07CSTH20RWColumn starting High byteRange: 0(651-windwidth)08CSTL80RWThe low 8 bit of column start position09WINHH11RWThe high 1 bit of win horizontal size.0AWINHL8E8RWThe low 8 bit of win horizontal size0BWINWH22RWThe high 2 bit of win vertical size0CWINWL888RWThe low 8 bit of win vertical size.0DPULSEMODE601RWPulse mode register.5 pulse_mode4:0 pulse width0EMODE8A0RWSensor mode register7 auto6 soc_clk_delay5 updown4 mirror3 evenskip2 strobe_en1 ad test0 column test0FVSPOS80RWVsync signal position7:5 control the St: X8the row number between Vsync posedge and hsync start.4:0 control the Et X8 the row number between Vsync negedge and hsync over.10COLBIAS625RWColumn bias adjustment register:11ADBIAS51CRWAD adjustment register:Addr(Hex)RegisterNameWidthDefault(Hex)R/WDescription12VARPD504RW3:0 DACs select 000: 0.24V 001: 0.36V 010: 0.48V 011: 0.60V 100: 0.72V (default) 101: 0.84V 110: 0.96V 111: 1.08V4 power-off 1: power on 0: power off of DAC, AD, BGAP, IO13TESTMODE80RWTest mode register.143FRESERVED40BENABLE187CRWFunction block enable control register1:7 Reserved6 RGB Gamma enable5 Edge enhancement enable4 Interpolation enable3 Defect removal enable2 Noise removal enable1 Lens-shading correction enable0 Linearity correction enable.41BENABLE289FRWFunction block enable control register2:7 HP mode6 Inverse color output5 Auto black level calibration4 Auto saturation enable3 AEC enable2 AWB enable.1 Skin correction enable0 Color correction enable42DEBUGMODE870RWISP mode register:7 ABC_mode6 AEC_mode5 AWB mode4 Noise removal mode:3 Output skin map2 Output edge map.1 Output defect map,0 ReservedAddr(Hex)RegisterNameWidthDefault(Hex)R/WDescription43OUTMODE1840RWOut mode control register1:7 RESERVED6 OPCLK output enable5 The edge to capture CISCTLs data.1: posedge 0: negedge4 ISP bypass 1: bypass ISP 0: go through ISP3 Output CIS_datas high 8bits or low 8bits when bypass ISP 1: high 8 bits 0: low 8 bits2 AD output mode when bypass ISP 1: select 0: no select1:0 AD output bit select44OUTMODE28E0Out mode control register2:7 ISP output high 8bits or low 8 bits1: high 8 bits 0: low 8 bits6 all output signals enable control1: output enable 0: output are high Z.5 average the neighbors Cb/Cr1: average 0: no average4:0 output bus data type setting5h00: CbYCrY5h01: CrYCbY5h02: YCbYCr5h03: YCrYCb5h06: RGB5655h07: RGBx5555h08: RGB555x5h09: RGBx4445h0a: RGB444x5h11: only Y5h12: only Cb5h13: only Cr5h14: only R5h15: only G5h16: only B45OUTMODE3824Out mode control register3:7:5 Subsample column ratio4:2 Subsample row ratio1:0 Input sequence46ISP_DEVID820ISPs slave device ID.474DRESERVEDAddr(Hex)RegisterNameWidthDefault(Hex)R/WDescription4ESYNCMODE823RWISP sync mode register:7 Skip AEC bad frame output6 Skip AWB bad frame output5 Skip sync-header in hsync4 OPCLK is gated in subsample1: gated 0: send out every OPCLK3 OPCLK gated in HBLANK2 OPCLK polarity1 HSYNC polarity1: high valid 0: low valid0 VSYNC polarity 1: high valid 0: low valid4FCAPSPEED523RWAEC and AWB capture speed control:5:4 AWB allow every N frame2h0 : every frame2h1 : every 2 frame2h2 : every 4 frame2h3 : every 8 frame 2:0 AEC allow every N frame2h0 : every frame2h1 : every frame2h2 : every 2 frame2h3 : every 3 frame2h4 : every 4 frame2h5 : every 5 frame2h6 : every 6 frame2h7 : every 7 frame50RESERVED51LC1820RWLC out value at 3252LC2840RWLC out value at 6453LC3860RWLC out value at 9654LC4880RWLC out value at 12855LC58A0RWLC out value at 16056LC68C0RWLC out value at 19257LC78E0RWLC out value at 22458RESERVED59OFFSETG1800RWG1 channel offset control. Range: -1281275AOFFSETR800RWR channel offset control.Range: -1281275BOFFSETB800RWB channel offset controlRange: -128127Addr(Hex)RegisterNameWidthDefault(Hex)R/WDescription5COFFSETG2800RWG2 channel offset control.Range: -1281275D60RESERVED61GAING1880RWG1 channel manual gain.62RESERVED63GAINR880RWR channel manual gain.64RESERVED65GAINB80B channel manual gain.66RESERVED67GAING280G2 channel manual gain.68RESERVED69CC11853RWColor correction parameter116ACC128F7RWColor correction parameter126BCC138F7RWColor correction parameter136CCC218F7RWColor correction parameter216DCC22853RWColor correction parameter226ECC238F7RWColor correction parameter236FRESERVED70LSCRBH20RWLens correction parameter1 on R channel71LSCRBL810RWLens correction parameter2 on R channel72LSCGBH20RWLens correction parameter1 on G channel73LSCGBL810RWLens correction parameter2 on G channel74LSCBBH20RWLens correction parameter1 on B channel75LSCBBL810RWLens correction parameter2 on B channel76LSCRSTART828RWLens correction start point.77LSCHCENTER83cRWLens correction row center.78LSCVCENTER850RWLens correction column center797FRESERVED80DNSDB630RWDe-noise standard b parameter81DNSDBB630RWDe-noise standard b parameter on blue channel82DNCWEIGHT824RWDe-noise center weight parameter7:4 on blue channel3:0 on red and green channels83DDTH1814RWDe-defect threshold1Addr(Hex)RegisterNameWidthDefault(Hex)R/WDescription84DDTH2826RWDe-defect threshold285DDTH380ARWDe-defect threshold386DDNUM800RODefect point numbers87DNLRANGE92De-noise parameters for low range.88DITH150ARWDirection judgement threshold189DITH2404RWDirection judgement threshold28ARESERVED8BEDGE163FRWThe edge enhancement top limit.8CEDGE2822RWThe edge enhancement parameters7:4 the edge value minimum.3:0 edge effect.8DRGBBL880RWRGB black level offset.8FRESERVED90GAMMA081ARWGamma parameter 0.91GAMMA1824RWGamma parameter 1.92GAMMA2832RWGamma parameter 2.93GAMMA3852RWGamma parameter 394GAMMA486ERWGamma parameter 4.95GAMMA5882RWGamma parameter 5.96GAMMA6894RWGamma parameter 6.97GAMMA78A4RWGamma parameter 7.98GAMMA88BCRWGamma parameter 8.99GAMMA98D2RWGamma parameter 9.9AGAMMA108E4RWGamma parameter 10.9BGAMMA118F0RWGamma parameter 11.9CGAMMA128FCRWGamma parameter 12.9DABCBL80x40RWThe ABC parameters7:4 high boundary3:0 low boundary9EABCBTN820RWABC black target number.9FRESERVEDA0SATURATION80x40RWGlobal saturation.A1CONTRAST80x40RWGlobal contrast.A2SATCB80x20RWSaturation on CbA3SATCR80x20RWSaturation on CrA4HIGHBSTART8C0RWThe start point of high brightness for chrominance attenuation. A5HIGHBSLOPE802RWAttenuation slow rate of high endA6LOWBSTART860RWThe start point of low brightness for chrominance attenuation.A7LOWBSLOPE805RWAttenuation slow rate of low end.A8SKINBCEN8F4RWSkin center on Cb channel.A9SKINRCEN80CRWSkin center on Cr channel.Addr(Hex)RegisterNameWidthDefault(Hex)R/WDescriptionAASKINRH400RWHigh bit of skin radius square.ABSKINRL8F0Low bit of skin radius square.ACSKINBH8DCRWSkin color brightness high limit.ADSKINBL832RWSkin color brightness low limit.AESKINBC880RWSkin correction for CbAFSKINRC888RWSkin correction for CrB0BFRESERVEDC0AECSL820RWAEC statistic low range.C1AECSH8F0RWAEC statistic high range.C2TSNH820RWAEC target statistic number high 8 bits.C3TSNL800RWAEC target statistic number low 8 bits.C4TSNR201RWAEC target statistic number range.2b00: 5122b01: 25