EDA考试软件部分.doc

本文件是由贾俊杰(1-5) 郭智豪（6-10） 贾亚峰（11-15）等同学编写的，同学们下载之后再试着编译和仿真一下，以确保无误（如有问题可以直接跟我们说一下，我们会及时修改），更希望同学们只是参考该文件，根据本文件是着写一下自己的文件，同时祝同学们能考出好成绩。本文件仅限于本班同学使用，谢谢亲们能耐心的看完。软件部分：（程序演示）第一题（59进制）module bcd60(ENB,CLK,CLR,COUT,DATA,LOAD,DOUT);input ENB,CLK,CLR,LOAD;input7:0 DATA;output COUT;output7:0 DOUT;reg7:0 Q; always (posedge CLK or negedge CLR)/beginif(!CLR)/是清零键吗？ begin Q = 8h0;/是，则清零 endelse begin if(ENB) begin if(LOAD) Q=DATA; else begin if(Q3:0=4h9)beginQ3:0=4h0;/个位加1if(Q7:4=4h5) begin Q7:4=4h0;endelse Q7:4=Q7:4+1;/十位加1 end else Q3:0=Q3:0+1; end end else Q=Q; endend assign DOUT = Q; assign COUT=(Q3:0=4h9&Q7:4=4h5)?1:0); /进位输出 Endmodule第二题（24进制）module bcd24(ENB,CLK,CLR,DATA,COUT,LOAD,DOUT);input ENB,CLK,CLR,LOAD;input 7:0 DATA;output COUT;output7:0 DOUT;reg7:0 Q; always (posedge CLK or negedge CLR)/beginif(!CLR)/是清零键吗？ begin Q = 8h0;/是，则清零 endelse begin/. if(ENB) beginif(LOAD) Q=DATA;elsebeginif(Q3:0!=9)begin if(Q7:4=2)beginif(Q3:0=3)Q=0;elseQ3:0=Q3:0+1;end elseQ3:0=Q3:0+1;endelsebeginQ3:0=0;Q7:4=Q7:4+1;end endend else Q=Q; endend assign DOUT = Q; assign COUT=(Q3:0=4h4& Q7:4=4h2)?1:0; /进位输出 Endmodule第三题（50进制）module bcd50(ENB,CLK,CLR,COUT,DATA,LOAD,DOUT);input ENB,CLK,CLR,LOAD;input7:0 DATA;output COUT;output 7:0 DOUT; reg7:0 Q; always (posedge CLK or negedge CLR)beginif(!CLR) begin Q = 8h0; endelse begin if(ENB) begin if(LOAD) Q=DATA; else beginif(Q3:0=4h9)beginQ3:0=4h0;if(Q7:4=4h4)beginQ7:4=4h0;endelseQ7:4=Q7:4+1;/十位加1endelseQ3:0=Q3:0+1;/个位加1end end else Q=Q; end/.endassign DOUT = Q;assign COUT=(Q3:0=4h9& Q7:4=4h4)?1:0; /进位输出 Endmodule第四題（4位二进制计数器）module cnt4(clk,rst,en,load,data,q);input clk,rst,en,load;input 3:0 data;output 3:0 q;reg 3:0 q1;always (posedge clk or negedge rst)beginif(!rst) q1=0;else if(en)beginif(!load) q1=data;elsebegin if(q116) q1=q1+1; else q1=4b0000;endendendassign q=q1; Endmodule第五题（3位二进制）module cnt3b(clk,rst,en,load,data,q);input clk,rst,en,load;input 2:0 data;output 2:0 q;reg 2:0 q1;always (posedge clk or negedge rst)beginif(!rst) q1=0;else if(en)beginif(!load) q1=data;else begin if(q18) q1=q1+1; else q1=4b0000; endendendassign q=q1; Endmodule第六题（4-16）module four_16(qout,G1,G2,d,c,b,a);input G1,G2,d,c,b,a;output 15:0 qout;reg 3:0 din;reg 15:0 qout;always (din,G1,G2) begindin=d,c,b,a;if(G1) qout=16b1111111111111111;else if(G2) qout=16b1111111111111111;else if(din)case(din)4d0: qout=16b0111111111111111;4d1: qout=16b1011111111111111;4d2: qout=16b1101111111111111;4d3: qout=16b1110111111111111;4d4: qout=16b1111011111111111;4d5: qout=16b1111101111111111;4d6: qout=16b1111110111111111;4d7: qout=16b1111111011111111;4d8: qout=16b1111111101111111;4d9: qout=16b1111111110111111;4d10: qout=16b1111111111011111;4d11: qout=16b1111111111101111;4d12: qout=16b1111111111110111;4d13: qout=16b1111111111111011;4d14: qout=16b1111111111111101;4d15: qout=16b1111111111111110;default:qout=16b1111111111111111;endcaseendendmodule第七题（16-7）module yimaqi(clk,din,dout,en,qout);input clk,en;output 6:0 dout;output 6:0 qout;input 3:0 din;reg 6:0 qout,dout;always (posedge clk) begincase(din)4b0000: dout=7b0111111;4b00001: dout=7b0000110;4b0010: dout=7b1011011;4b0011: dout=7b1001111;4b0100: dout=7b1100110;4b0101: dout=7b1101101;4b0110: dout=7b1111101;4b0111: dout=7b0000111;4b1000: dout=7b1111111;4b1001: dout=7b1101111;4b1010:dout=7b1110111;4b1011:dout=7b1111100;4b1100:dout=7b0111001;4b1100:dout=7b1011110;4b1110:dout=7b1111001;4b1111:dout=7b1110001;endcaseendalways (dout) begincase(dout)dout=7b0111111:qout=0;dout=7b0000110:qout=1;dout=7b1011011:qout=2;dout=7b1001111:qout=3; dout=7b1100110:qout=4;dout=7b1101101:qout=5;dout=7b1111101:qout=6;dout=7b0000111:qout=7;dout=7b1111111:qout=8;dout=7b1101111:qout=9;dout=7b1110111:qout=hA;dout=7b1111100:qout=hB;dout=7b0111001:qout=hC;dout=7b1011110:qout=hD;dout=7b1111001:qout=hE;dout=7b1110001:qout=hF;endcaseendendmodule第八题（3-8）module three_8(din,dout);input 2:0 din;output 7:0 dout; reg 7:0 dout;always (din) begincase(din) 3d0:dout=8b10000000;3d1:dout=8b01000000;3d2:dout=8b00100000;3d3:dout=8b00010000;3d4:dout=8b00001000;3d5:dout=8b00000100;3d6:dout=8b00000010;3d7:dout=8b00000001;endcaseendendmodule第九题（4-1选择器）module four_c_one(a,b,c,d,s1,s0,y);input a,b,c,d,s1,s0;output y;reg y;always (a,b,c,d,s1,s0) begincase(s1,s0)2b00:y=a;2b01:y=b;2b10:y=c;2b11:y=d;default:y=a;endcaseendendmodule第十題（4位全加器）module four_adder(a,b,cin,cout,dout);output 3:0 dout;output cout;input 3:0 a,b;input cin;assign cout,dout=a+b+cin;endmodule第十一题（10分频）module fenpinqi10(reset,clkin,clkout,qout); input reset,clkin; output clkout,qout; reg clkout; reg3:0 qout; always (posedge clkin) begin if(!reset) qout=0; else if(qout9) qout=qout+1; else qout=0; end always (posedge clkin) begin if(!reset) clkout=0; else if(qout=9) clkout=1; else clkout=0; end endmodule第十二题（8分频）module fenpinqi8(reset,clkin,clkout,qout); input reset,clkin; output clkout,qout; reg clkout; reg2:0 qout; always (posedge clkin) begin if(!reset) qout=0; else qout=qout+1; end always (posedge clkin) begin if(!reset) clkout=0; else if(qout=7) clkout=1; else clkout=0; end endmodule第十三题（移位寄存器）module yiweijicunqi(clk,c0,md,d,qb,cn);output cn; output 7:0 qb;input clk,c0;input7:0 d; input2:0 md;reg7:0 REG; reg cy;always(posedge clk) begincase(md)1:begin REG0=c0; REG7:1=REG6:0; cy=REG7 ;end /左移2:begin REG0=REG7; REG7:1=REG6:0; end /循环左移3:begin REG7=REG0; REG6:0=REG7:1;end /循环右移4:begin REG7=c0; REG6:0=REG7:1; cy=REG0 ;end /右移5:begin REG=d;end /赋值default:begin REG=REG; cy=cy;endendcase endassign qb=REG; assign cn=cy;Endmodule第十四题（4位乘法器）module chengfaqi4(r,b,a);parameter s=4;output 2*s:1 r;input s:1 a,b;reg2*s:1 r;integer i;always(a or b)beginr=0;for(i=1;i=s;i=i+1)if(bi) r=r+(a(i-1);endEndmodule第十五题（优选8-3编码器）module bianmaqi