差分信号(collected by 19245068).ppt

12 4 2002 DifferentialSignaling IntroductionReadingChapter6 12 4 2002 DifferentialSignaling Agenda DifferentialSignalingDefinitionVoltageParametersCommonmodeparametersDifferentialmodeparametersCurrentmodelogic CML bufferRelatetoparametersModeling simulationTimingparametersClockrecoveryEmbeddedclockACcouplingCommonmoderesponseIssueswithsimulation8B10BencodingDCbalancedcodesDutyCycledistortionCycle 12 4 2002 DifferentialSignaling SingleEndedSignaling Allelectricalsignalcircuitsrequirealooporreturnpath Singleendedsignalsubjectseveralmeansofdistortionsandnoise Groundorreferencemaymoveduetoswitchingcurrents SSOnoise Wetouchedonthisinthegroundconundrumclass Asingleendedreceiveronlycaresaboutavoltagethatisreferencedtoitsownground Electromagneticinterferencecanimposevoltageonasingleendedsignal Signalpassingfromoneboardtoanotheraresubjecttothelocalgrounddisturbance Wecancounteractmanyoftheseeffectbyaddingmoreground Asfrequenciesincreasebeyond1GHz 80 ofthesignalwillbelost 12 4 2002 DifferentialSignaling Reviewofthresholdsensitivity ThewaveisreferencedtoeitherVccorVss ConsequentlytheeffectiveDCvalueofthewavewillbetiedtooneoftheserails ThewaveisattenuatedaroundtheeffectiveDCcomponentofthewaveform butthereferencedoesnotchangeaccordingly Hencetheclocktriggerpointbetweenvariousclockloadpointsisverysensitivetodistortionandattenuation Tx 12 4 2002 DifferentialSignaling DifferentialSignaling Anysignalcanbeconsideredaloopiscompletedbytwowires Oneofthe wires insingleendedsignalingisthe groundplane DifferentialsignalingusestwoconductorsThetransmittertranslatesthesingleinputsignalintoapairofoutputsthataredriven180 outofphase Thereceiver adifferentialamplifier recoversthesignalasthedifferenceinthevoltagesonthetwolines AdvantagesofdifferentialsignalingcanbesummedupasfollowsDifferentialSignalingisnotsensitivetoSSOnoise Adifferentialreceiveristolerantofitsgroundmovingaround Ifeach wire ofpairisoncloseproximityofoneandother electromagneticinterferenceimposesthesamevoltageonbothsignals Thedifferencecancelsouttheeffect SincetheACcurrentsinthe wires areequalbutoppositeandproximal radiatedEMIisreduced Signalspassingfromoneboardtoanotherarenotsubjecttothelocalgrounddisturbances Asfrequenciesincreasebeyond1GHz upto80 ofthesignalmaybelost butdifferencestillcrosses0volts Therearestilllossissuesfordifferentialsignalingbutonlycomeintoplayinhighlosssystem Mostsingleendedsystemsassumeapproximately15 channelloss 12 4 2002 DifferentialSignaling DifferentialSignaling Cons Thecostisdoublingthesignalwires butthismaynotbesobadascomparedtoaddinggroundstoimprovesingleendedsignaling Routingconstraint Pairsignalsneedtoberoutedtogether Differentialsignalhavecertainsymmetryrequirementsthatmayposeroutingchallenges 12 4 2002 DifferentialSignaling DifferentialSignalParameters Voltageonline1 aVoltageonline2 bDifferentialvoltaged a bCommonmodevoltagec a b 2Oddmodesignal o a b 2Evenmodesignal e a b 2Signalonline1a e oSignalonline2b e oUsefulrelations o b 2 e c Line1 Line2 Reference 12 4 2002 DifferentialSignaling PropagationTermstoConsider DifferentialmodepropagationCommonmodepropagationSingleendedmode uncoupled propagationThisiswhentheotherlineisnotdrivenbutterminatedtoabsorbedreflections Transmissionlinematrixeswillreflectthesemodes 12 4 2002 DifferentialSignaling DifferentialMicrostripExample SE singleended uncoupled 12 4 2002 DifferentialSignaling DifferentialImpedance CouplingbetweenlinesinapairalwaysdecreasesdifferentialimpedanceDifferentialimpedanceisalwayslessthat2timestheuncoupledimpedanceDifferentialimpedanceofuncoupledlinesis2timestheuncoupledimpedance 12 4 2002 DifferentialSignaling PropagationVelocities ForTEMstructures striplines Differentialmode CommonMode andsingleendedvelocitiesarethesameForNonTEMandQuasi TEMstructures microstrip Differentialmode CommonMode andsingleendedvelocitiesandimpedancesarenotthesame Commonmodecanbeconvertedtodifferentialmodeatareceiverandresultinadifferentialsignaldisturbance 12 4 2002 DifferentialSignaling ExampleofCommonMode Line1andline2havethesameDCoffset ThisisDCcommonmode ItcanbedefinedasanaverageDCfortimedurationofmanyUIcyclesvalueaswell Line1andline2havethesameACoffsetThisisACcommonmodeACcommonmodealsoresultfromtimedifferences skew betweensignalonline1andline2 ThiscanresultinACcommonmodeanddifferentialsignalloss Thefollowingslidewillbeusedtoclarifytheabove 12 4 2002 DifferentialSignaling DifferentialSignalingBasics Forlongchannels atGHzfrequencies signaltendlooklikesinewaves Theartificialoffsetcommontoline1and2hasanaverageof1andvariesaroundthataverageby 0 1inaperiodmanor 12 4 2002 DifferentialSignaling Individualsignals Devicesneedtohaveenoughcommonmodedynamicvoltagerangetoreceiveortransmitthewaveforms Inthiscasethesignalsswingbetween 0 1and2 1 Thesinewaveamplitudeis1andpeaktopeakis2 Signalaandbiswhatwouldbeobservedwith2oscilloscopeprobes 12 4 2002 DifferentialSignaling DifferentialModeSignal Thedifferentialamplitudeis2andpeaktopeakis4whichis2timestheindividualsignalpeaktopeakamplitude Noticethedistortionsaregone 12 4 2002 DifferentialSignaling CommonModeSignal TheDCcommonmodesignalis1TheACcommonmodesignalis 2vpeaktopeakSomemayspecificationsmaycallthis0 1vpeakfromtheDCaverageWewilladdthiscommonmodetothesignals a and b 12 4 2002 DifferentialSignaling Add150psskewtosignalb Waveformsdonotlooksogood Weevenhavewhatappearstobenon monotonicbehavior 12 4 2002 DifferentialSignaling DifferentialsignallooksOK Howeverwelostdifferentialsignalamplitude Itusedtobe4peaktopeakandnowis3 562 12 4 2002 DifferentialSignaling Commonmodemeasurementsaredifferent Averageisstill1 Peaktopeakis0 944butpeakis0 504ACcommonmodesignalscanbeconvertedtodifferential 12 4 2002 DifferentialSignaling PWBstructuresthatintroduceSkew 12 4 2002 DifferentialSignaling Bendsintroduceskew Backtobackbendscompensateforskewfromfrequenciesbelow2GHz Backtobackbendscompensateforskewfromfrequenciesbelow2GHz 12 4 2002 DifferentialSignaling MoreTerms BalancedandUnbalanced GoodAgilentTechnologiesarticleonbalanceandunbalancedsignaling 12 4 2002 DifferentialSignaling Ethernet10 100BASE Texample 50W 50W 50W 50W Transformer Filter Common modechoke Unbalanced Balanced 12 4 2002 DifferentialSignaling LowVoltageDifferentialSignaling LVDS 200MHz 500MHzRangePublishedbyIEEEin1995LacksrobustnessforGHzSignalingWellsuitedistributingsystemclocksGoodnoisemarginCommonmodeimpedancehaswiderangeprovidebufferdesignflexibilityDifferentialimpedanceisoptimizearound100WDifferentialreceiverswitchingthresholdsaretighterthanforsingleendedlogic MostdevicerequireexternalterminationandbiasresistorsDoesnothavecapacitanceorpackagespec ThisseverelylimitsGHzoperation 12 4 2002 DifferentialSignaling CurrentModeLogic EmergingtechnologyNorealspecyetbutcaninferoperationfromspec slikePCIExpress Infiniband USB SATA etc TxandRxlinesareseparateTheTxdriversteerscurrentbetweenthedifferentialterminalsACcouplingbetweenTxandRxwithaseriescapacitorprovidescommonmodedesignflexibilityTerminationisinbuffers Thismayrequirecompensationorabandgapreferencetoinsureatightresistancerange 12 4 2002 DifferentialSignaling ExampleofSimpleCMLDifferentialBehavioralCircuit Vcc Vss I source r termn C term r termp C term PositiveTerminal NegativeTerminal Thisexponentdetermineswaveshape Thisswitchtimeoffset BalancebetweenforFETswitch 2ndlecture 12 4 2002 DifferentialSignaling ExampleofSensitivities I balance C Moreprominentforfasteredges 12 4 2002 DifferentialSignaling ExampleofSensitivities Slew Skew R skew R Fslew 12 4 2002 DifferentialSignaling SerialDifferential GHztransmissionwillhavemanyUI sofdataintransitontheinterconnectatanypointsintime Henceitbecomesusefultothinkofthisasserialdatatransmission Oftenmultiplesinglechannelsaregangedinparalleltoachieveevenhigherdatathroughput 12 4 2002 DifferentialSignaling ACcouplingissues Seriescapacitorscanbuildupchargedifferencebetweendifferentialterminalsforthefollowingreasons UnequalnumbersoffzeroandonesDutycycle UI distortion Thesolutionistouseadatacodethatis DC balanced 8B10B 8bit10bit withdisparityisonesuchcodeTightUIcontrolisabasicrequirementforkeepingthesignaleyeopen 12 4 2002 DifferentialSignaling EyeDiagram Theeyediagramisaconvenientwaytorepresentwhatareceiverwillseeaswellasspecifyingcharacteristicsofatransmitter TheeyediagrammapsallUIintervalsontopofoneandother Theopeningineyediagramismeasureofsignalquality Thisisthesimplesttypeofeyediagram Theareotherformwhichwewilldiscusslater EyeDiagram 12 4 2002 DifferentialSignaling Creatingeyediagram Plotperiodicvoltagetimeramps sawtoothwaves onxversesthevoltagewaveonY CanbedonewithAvanwavesexpressioncalculatorandcanbesavedinaconfigurationfile 12 4 2002 DifferentialSignaling Createrampwithexpressionbuilder Startofrelativeeyeposition Timeofeyestart UnitInterval 12 4 2002 DifferentialSignaling CopyRamptoXAxis UsemiddlebuttontodragramptoCurrentX Axis 12 4 2002 DifferentialSignaling Voltageandperiodvolt timeramp 12 4 2002 DifferentialSignaling Clocking Theonethingomittedinthesuggestsinthepreviousslidesoneyediagramswasthe chop frequency WeassumeditwasUI Thisissimpleforsimulation Timemarchesalongandallsignalsstartoutsynchronizedintime ThisisnottrueforrealmeasurementsinceedgeswillsignificantlyjitterandmakeitdifficulttodeterminatewheretheexactUIispositioned Presently therearebasicallytwoformsofGHz clockingEmbeddedclockingForwardedclocking 12 4 2002 DifferentialSignaling Embeddedclocking ThiswhatisusedinFiberChannel GigabitEthernet PCIExpress Infiniband SATA USB etc TheclockisextractedfromthedataThereisrequirementthatdatatransitionsareataminimumrate 8B 10Bguaranteesthis Wediscussthisinmoredetaillater Aphaseinterpolatorisnormallyusedtoextracttheclockfromthedata Wediscussedthephaseinterpolatorintheclockingclass ThephaseinterpolatoristiedtothePCIExpress likejitterspec MedianandJitteroutlier 12 4 2002 DifferentialSignaling JitterMedianandOutlierSpec EyeopeningisdefinedfromastableUI JittermedianusedtodetermineastableUIItisusedasareferencetodetermineeyeopeningJitterOutlierisusedtoguaranteelimitsofoperation JitterMedian Jitteroutlier Eyediagram UI 12 4 2002 DifferentialSignaling ForwardedClocking TheTxclockissourcedandreceiveddownstream TheclockisaTxdatabuffersynchronizedwiththeTxdatabits Asynchronizationortrainingsequenceonadatalineisusedtoadjustthereceiverclocksothatitisinphasesynchronizationwiththedata Thecaveatisthattheactualdataclocklagstherealdatabyafewcycles ThewholeideaisthatthejitterintroducedoverthesecycleswouldbesmallerthanthejitterassociatedwithtwothePLLsusedtoprovidebaseclocksforanembeddedclockdesign 12 4 2002 DifferentialSignaling AspectsofACcoupling WewillexploreissueswithACcouplingwithasimulationexample FirstwewillcreateasimpleCMLdifferentialmodelNextwewilltieittoadifferentialtransmissionlineandaterminator Assignment7istoreproducetheseeffectswithaHSPICEprogram TheoutputAvanwaveswithapowerpointstorysummarywhatyouwillhandin Thebasisforourworkwillbelastsemesterstestckt spdeck 12 4 2002 DifferentialSignaling BehavioralDataModel Example 12bitofrepeatingdata010101001001 v t data UI 500psTr Tf 100ps Rterm 50Cterm 0 25pf Vswing 800mV I Vswing 50 50 2 Waveshape Refertofirstcourse 3rdlecture 12 4 2002 DifferentialSignaling ACcoupledDifferentialCircuit ACcouplingcapsarenormallylarger butarescaleddowntoillustratecommonmodeeffects 12 4 2002 DifferentialSignaling TopLevelHSPICECODE Modified Convenience 12 4 2002 DifferentialSignaling NoinitialconditionsonDCblockingcaps 300nsofsimulationtime Cblknpkg2 nbpkg2 n1nf ic 400mvCblkppkg2 pbpkg2 p1nf ic 400mv101010101010repeating12bitpattern Differential Singleended Reproducethisatpackage2 receiver 12 4 2002 DifferentialSignaling SetICtoVswing 2 Differential Singleended Reproducethisatpackage2 receiver 12 4 2002 DifferentialSignaling Notcompletelyfixed InitialvoltageforD andD isnot0sothereisastepresponsewhenthewavereachesthereceiver Wecanfixthisbymultiplyingboth n and p controlwavesfortheVCR voltagecontrolledresistor by0forthefirstcycle ThisforcestheDCsolutionattheotherendofthelineto0voltsdifferential 12 4 2002 DifferentialSignaling Insurebothlegsstartatsamevoltage Qualifyingvoltage Qualifyingvoltagepcontrolvoltage Qualifyingvoltagencontrolvoltage 12 4 2002 DifferentialSignaling Results Prettygood Differential Singleended Reproducethisatpackage2 receiver Mayhavetoignorefirst1 2cycles 12 4 2002 DifferentialSignaling Nowletschangebitpattern 100000001010ThepatterncreatesaDCchargetobebuiltupinthecapThesolutionistocreateacodethathasequalamountof1 sandzeros Thisistherationalfor8bit10bit 8b10b coding Differential Singleended Reproducethisatpackage2 receiver 12 4 2002 DifferentialSignaling CrossingOffset Thecrossingoffsetisthehorizontallinethatisintheverticalcenteroftheeyeanditshouldbeat0voltsforadifferentialsignal TheamountofoffsetistheaverageDCvalue Asimpleapproximationisoneminustheratioofone stozerostimesthereceivedvswing 2 Thisdoesnotincludededgeshapeeffects 12 4 2002 DifferentialSignaling Repeatpatternsof5onesand6zeros Approx offset Reproducethisatpackage2 receiver Hint starteyediagramat200ns 12 4 2002 8b 10bencodingandbackground CourtesyofScottGardiner Intel 12 4 2002 DifferentialSignaling 8b 10b SimpleScheme Theencodingiscomprehendedinasetoftableswhichconformtoasetofpredetermined rules HelpfulHint Completetablesthatgivealltheliteral10bencodingsdoexist andtheycomprehendalloftheencodingrules 8bitsareencodedinto10bits 12 4 2002 DifferentialSignaling 8b 10b Overview The10bitsarereferredtoasa symbol ora code group Theoriginal8bitsarebrokenintoa3bitblockanda5bitblock eachofthesearecalledsub blocks F1 11110001The3bitsub block labeledHGF isencodedinto4newbits labeledfghj notethattherelativeorderandpositionofthesub blocksisswitcheduponencodingHGFEDCBA abcdeifghjHence anextrabit j isaddedtothenewlyencoded3bitblockandanextrabit i totheencoded4bitblockcreatinga4and5bitsub blocks 12 4 2002 DifferentialSignaling 8b 10b CharacterConventions BothDataCharactersandSpecialControlCharactersexist nomenclature D a b K a b D K SignifiesDataorControla 5bitblocktobeencodedb 3bitblocktobeencodedSetofAvailableDataandControlCharactersData D a b D0 0 D31 0 D0 1 D031 1 D0 7 D31 7All256Possible8 bitDatacharacters 00throughFFHEX Control K a b K28 0 K28 7 K23 7 K27 7 K29 7 K30 7 12 4 2002 DifferentialSignaling 8b 10b DCbalancing Disparity Nevermorethan5consecutive1 sor0 sallowedinarow consecutively i e themaximum runrate is5tomaintainaDCbalancedtransmission Thisguaranteesthelowestfrequencytobe1 10ofthemaxfrequency i e only1decadedatabandwidthrequired With8b 10b eitherpositive RD ornegative RD disparityencodingispossible 12 4 2002 DifferentialSignaling 8b 10b Disparity Disparityis thedifferencebetweenthenumberofonesandzeros positiveandnegativedisparityrefertoanexcessofonesorzerosrespectively Note neutraldisparityissaidtooccurwhenRD andRD encodingareidentical meaningtheywilleachhavethesamenumberofonesandzeros therearesomeexceptions Agivensub blockorsymbolcanhaveanactualdisparitynumberofeitherazero neutral 2or 2 thoughtheRunningDisparityissaidonlytobePositive NegativeorNeutral 12 4 2002 DifferentialSignaling 8b 10b RunningDisparity TheRunningorCurrentDisparity abinaryvalueof or istrackedbytheTX RXandiscomputedateverysub blockboundaryandateachsymbolboundary Thevaluefromonesub blockorsymbolisusedwiththatofthenextsub blockorsymboltogivea running or current status 12 4 2002 DifferentialSignaling 8b 10b RunningDisparityAlgorithm Foragivenencodingofabyte thestartingdisparityiswhatexistedattheendoftheprevioussymbolTherunningdisparityisthencalculatedfirstforthe6bitsub block comprehendingthestartingdisparityvalue The6bitsubblockdisparityvalueisthenusedasthestartingdisparitywhentherunningdisparitycalculatedforthe4bitsub blockTherunningdisparityfortheentire10bitsymbolisnowthesameastherunningdisparityfoundattheendofthe4bitsub block andtherunningdisparityatthebeginningofthenextsymbol 6bitsub blockisthesameasthatfoundattheendofthethissymbol Again agivensub blockorsymbolcanhaveanactualdisparitynumberofeitherazero neutral 2or 2 thoughtheRunningDisparityisonlysaidtobePositive NegativeorNeutral 12 4 2002 DifferentialSignaling 8b 10b RunningDisparityCalculationAlgorithm Assumptions The8bto10bencodinghasalreadybeendone AcurrentdisparityvalueisalreadyassumedProcess Calculatethedisparityfortheleftmost6bitsfirst keepinginmindthecurrentdisparityvaluebeforeenteringthealgorithm Thencalculatethedisparityfortherightmost4bitskeepinginmindthedisparityvaluedeterminedafteranalyzingtheprevious6bits Thedisparityforboththe6 bitandthe4 bitblocksshouldbecalculatedasfollows 12 4 2002 DifferentialSignaling 8b 10b RunningDisparityCalculationMethod Method If of1 s 0 sDisparity Positive 1 Elseif of0 s 1 sDisparity Negative 0 Elseif6 bit 000111ThenDisparity Positive 1 Elseif6 bit 111000ThenDisparity Negative 0 Elseif4 bit 0011ThenDisparity Positive 1 Elseif4 bit 1100ThenDisparity Negative 0 ElseDisparity Disparity ifnoneoftheabove thenthedisparityvaluedoesn tchange Note Assumingaencoding more1 sacrosstheentire10bcodeyieldspositivedisparity more0 syieldsnegativedisparity andeven sof1 sand0 syieldsneutraldisparity i e disparityisthesameasitwasbefore 12 4 2002 DifferentialSignaling 8b 10b Disparity EncodingExample Transmitterkeepsrunningtrackofcurrentdisparity itiseitherRD RD orneutral NeutralmeansthedisparitytrackerkeepsthepreviousRD orRD valueARunningDisparityofRD isalwaysfollowedbyanRD encodingandviceversaIfRunningDisparityisRD thefollowingisencodedforthedatabyteF1 HGFEDCBA abcdeifghj11110001 1000110111 RD encoding IfRunningDisparityisRD thefollowingisencodedforthedatabyteF1 HGFEDCBA abcdeifghj11110001 1000110001 RD encoding 12 4 2002 DifferentialSignaling 8b 10b Disparity EncodingExample Notethatthenumberofonesandzerosinthecurrentlychosenencodingworkstobalanceouttheoffsetinthenumberofonesandzeroes trackedbytheRunningDisparityvalue fromthepreviousencodingI E Don tconfusethedefinitionofPositiveDisparitywiththeRD encodingchoice PositiveDisparitymeansthereisacurrentrunningtotalofmoreonesthanzeros Thus anRD encodinggenerallyhasmorezerosthanones Alsonotethatitispossiblethatthe4 bitsub blockofaRD orRD symbolencodingcanyieldanegativeorpositivedispa