DE2 实验练习解答—lab 1 (Digital Logic) (DE2) (Quartus II).docx

/halflife/archive/2010/03/12/1684764.htmlAbstractSwitches、Lights and Multiplexers Release: 1.0 By yf.x 03/12/2010 Introduction这个练习的目的是学习如何连接简单的输入、输出设备到一个FPGA芯片，并且用这些器件实现一个电路。我们将用DE2开发板上的switches SW17-0作为输入，用LED和7-segment displays作为输出。 完成DE2 实验练习1（Digital Logic）对与初学者来说是一个比较大的实验。我估计，每天要花几小时才能完成。这个实验包括6个部分，主要是组合逻辑电路和使用assign语句。 Part I ：第一次使用assign语句Altera 的DE2开发板有18个拨动开关（toggle switch）和18个红色的LED。Part I非常简单，在实验手册里首先介绍了Verilog的格式，并给出了代码。需要自己做的部分就是把代码粘贴到Quartus II然后运行。当你拨动一个开关（比如Switch 1），对应的LED就会亮（比如LEDR1），这部分在实验手册里解释的很详细。 Part 1代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part1.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use Switch and led 10 11 Release : 03/05/2010 1.0 12 13 */ 14 15 /Simple module that conects the SW switchs to the LEDR lights 16 17 module part1(SW,LEDR); 18 19 input 17:0 SW; /toggle switches 20 21 output 17:0 LEDR; /red leds 22 23 assign LEDR=SW; 24 25 endmodulePart II：设计一个8位的2选1多路选择器用Verilog设计一个多路选择器有很多种方法。但是在这个实验里，要求只能用门级电路描述。比如：assign m=(s&x)|(s&y);这里x和y是输入，s是选择信号，m是输出。X被定义为SW 0到7，Y被定义为SW 8到15，S被定义为SW17，M被定义为绿色的LEDG 0到7.这部分的完整代码如下。 Part II 代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part2.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use assign statements 10 11 Release : 03/05/2010 1.0 12 13 */ 14 15 /Top level file of part2 16 17 module part2(LEDR,LEDG,SW); 18 19 input 17:0SW; 20 21 output 17:0LEDR; 22 23 output 7:0LEDG; 24 25 wire s; 26 27 wire 7:0X,Y,M; 28 29 assign S=SW17; 30 31 assign X=SW7:0; 32 33 assign Y=SW15:8; 34 35 assign LEDR=SW; 36 37 assign LEDG=M; 38 39 mux2to1 m7(S,X7,Y7,M7); 40 41 mux2to1 m6(S,X6,Y6,M6); 42 43 mux2to1 m5(S,X5,Y5,M5); 44 45 mux2to1 m4(S,X4,Y4,M4); 46 47 mux2to1 m3(S,X3,Y3,M3); 48 49 mux2to1 m2(S,X2,Y2,M2); 50 51 mux2to1 m1(S,X1,Y1,M1); 52 53 mux2to1 m0(S,X0,Y0,M0); 54 55 endmodule 56 57 /1-bit 2-to1 multiplexer 58 59 module mux2to1(s,x,y,m); 60 61 input s,x,y; 62 63 output m; 64 65 assign m=(s&x)|(s&y); 66 67 endmodule 68 69 在我的代码里，有一个小技巧。我把RTL代码分成2部分。1个主模块和1个多路选择器模块。通过调用多选器模块，可以很容易的实现设计。（这里因为用到很多引脚，为了方便引脚分配，输入、输出端口名和板上的器件名相同。） Part III：设计一个3位的5选一多路选择器设计一个3位的5选1多路选择器很简单。如图1所示，使用了4个3位的2选1的多路选择器。完整代码如下： 图 1 5选1多路选择器 Part III 代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part3.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use assign statements 10 11 Release : 03/05/2010 1.0 12 13 */ 14 15 /3BIT 5 to 1 Multiplexer Module 16 17 module mux_3bit_5to1(S,U,V,W,X,Y,M); 18 19 input2:0S,U,V,W,X,Y; 20 21 output2:0M; 22 23 wire2:0m0,m1,m2; 24 25 / Leftmost 2 to 1 Multiplexers 26 27 /Top 28 29 assign m00 = (S0&U0)|(S0&V0); 30 31 assign m01 = (S0&U1)|(S0&V1); 32 33 assign m02 = (S0&U2)|(S0&V2); 34 35 /Bottom 36 37 assign m10 = (S0&W0)|(S0&X0); 38 39 assign m11 = (S0&W1)|(S0&X1); 40 41 assign m12 = (S0&W2)|(S0&X2); 42 43 /Middle Multiplexer 44 45 assign m20 = (S1&m00)|(S1&m10); 46 47 assign m21 = (S1&m01)|(S1&m11); 48 49 assign m22 = (S1&m02)|(S1&m12); 50 51 /Last Multiplexer 52 53 assign M0 = (S2&m20)|(S2&Y0); 54 55 assign M1 = (S2&m21)|(S2&Y1); 56 57 assign M2 = (S2&m22)|(S2&Y2); 58 59 endmodule 60 61 part IV：设计一个7segment 显示“HELLO”这部分要求用一个7segment显示H、E、L、O。需要注意DE2上的七段码数码管是共阴极，对应的真值表见表 1 7-segment 译码真值表： c2c1c0character7_segment000H1001000001E0110000010L1110001011O0000001100blank1111111101110111表 1 7-segment 译码真值表 表达式化简，用卡诺图，比如seg6（上表7-segment的最右边的一列），化简过程如下图所示：Part IV：代码 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part4.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use 7segment display 10 11 Release : 03/12/2010 1.0 12 13 */ 14 15 /use a 7segment display H、E、L、O 16 17 module part4(SW,LEDR,HEX0); 18 19 input 2:0 SW; 20 21 output 2:0 LEDR; 22 23 output 0:6 HEX0; 24 25 assign LEDR=SW; 26 27 /Seven Segment Decoder for HELO 28 29 assign HEX00 = SW2|SW0; 30 31 assign HEX01=SW2|(SW1&SW0)|(SW1&SW0); 32 33 assign HEX02=SW2|(SW1&SW0)|(SW1&SW0); 34 35 assign HEX03 = SW2|(SW1&SW0); 36 37 assign HEX04 = SW2; 38 39 assign HEX05 = SW2; 40 41 assign HEX06 = SW2|SW1; 42 43 endmodule 44 45 注：因为要求用连续赋值语句和布尔逻辑实现，对于七段码的每一段的表达式都可以根据真值表先化简（当然综合工具会自动化简，但是如果考综合工具化简，每个表达式就会很长）。化简就会用到我们学过的卡诺图图（以前一直觉得卡诺图用不上L）。Part V：用5个7segment循环显示HELLO这部分要求用5个数码管循环显示HELLO,涉及part III和part IV的引用。5个数码管循环显示如图2. 图 2 数码管循环显示HELLO Part V 代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part5.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to rotating display 10 11 Release : 03/12/2010 1.0 12 13 */ 14 15 /Top level file 16 17 module part5(SW,HEX4,HEX3,HEX2,HEX1,HEX0); 18 19 input 17:0SW; 20 21 output 0:6 HEX4,HEX3,HEX2,HEX1,HEX0; 22 23 wire 2:0 M4,M3,M2,M1,M0; 24 25 mux_3bit_5to1 N4(SW17:15,SW14:12,SW11:9, 26 27 SW8:6,SW5:3,SW2:0,M4); 28 29 mux_3bit_5to1 N3(SW17:15,SW11:9,SW8:6, 30 31 SW5:3,SW2:0,SW14:12,M3); 32 33 mux_3bit_5to1 N2(SW17:15,SW8:6,SW5:3, 34 35 SW2:0,SW14:12,SW11:9,M2); 36 37 mux_3bit_5to1 N1(SW17:15,SW5:3,SW2:0, 38 39 SW14:12,SW11:9,SW8:6,M1); 40 41 mux_3bit_5to1 N0(SW17:15,SW2:0,SW14:12, 42 43 SW11:9,SW8:6,SW5:3,M0); 44 45 char_7seg H4(M4,HEX4); 46 47 char_7seg H3(M3,HEX3); 48 49 char_7seg H2(M2,HEX2); 50 51 char_7seg H1(M1,HEX1); 52 53 char_7seg H0(M0,HEX0); 54 55 endmodule 56 57 /implements a 7_segment decoder for H,E,L,O,and blank 58 59 module char_7seg(c,display); 60 61 input 2:0c; 62 63 output 0:6display; 64 65 /Seven Segment Decoder for HELO 66 67 assign display0 = c2|c0; 68 69 assign display1 = c2|(c0&c1)|(c1&c2&c0); 70 71 assign display2 = c2|(c0&c1)|(c0&c1&c2); 72 73 assign display3 = c2|(c1&c0); 74 75 assign display4 = c2; 76 77 assign display5 = c2; 78 79 assign display6 = c2|c1; 80 81 endmodule 82 83 /3BIT 5 to 1 Multiplexer Module 84 85 module mux_3bit_5to1(S,U,V,W,X,Y,M); 86 87 input2:0S,U,V,W,X,Y; 88 89 output2:0M; 90 91 wire2:0m0,m1,m2; 92 93 / Leftmost 2 to 1 Multiplexers 94 95 /Top 96 97 assign m00 = (S0&U0)|(S0&V0); 98 99 assign m01 = (S0&U1)|(S0&V1); 100 101 assign m02 = (S0&U2)|(S0&V2); 102 103 /Bottom 104 105 assign m10 = (S0&W0)|(S0&X0); 106 107 assign m11 = (S0&W1)|(S0&X1); 108 109 assign m12 = (S0&W2)|(S0&X2); 110 111 /Middle Multiplexer 112 113 assign m20 = (S1&m00)|(S1&m10); 114 115 assign m21 = (S1&m01)|(S1&m11); 116 117 assign m22 = (S1&m02)|(S1&m12); 118 119 /Last Multiplexer 120 121 assign M0 = (S2&m20)|(S2&Y0); 122 123 assign M1 = (S2&m21)|(S2&Y1); 124 125 assign M2 = (S2&m22)|(S2&Y2); 126 127 endmodule 128 129 技巧：同样的选择参数被用于不同的多路选择器实例引用，不同的多路选择器连接不同的数码管，每个数码管都可以循环显示不同的字符。前两部分的代码稍稍修改就可直接引用。 Part VI：用8个数码管循环显示HELLO要求按照图 3 数码管循环显示，这是整个实验最复杂的部分，需要用到前5部分的信息。因为要用到选择信号的8中状态，需要创建一个8选1的多路选择器。其余就类似第5部分。注意在实例引用8选1多路器时8个输入信号的排列（我的神啊，眼睛差点都看花了J）! 图 3 数码管循环显示 Part VI 代码： 1 /* 2 3 (C) yf.x 2010 / 4 5 Filename : part6.v 6 7 Compiler : Quartus II 9.1 Web Edition 8 9 Description : Demo how to use 8 7seg rotating display 10 11 Release : 03/12/2010 1.0 12 13 */ 14 15 /Top level file 16 17 module part6(SW,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2, 18 19 HEX1,HEX0); 20 21 input 17:0SW; 22 23 output 0:6HEX7,HEX6,HEX5,HEX4,HEX3,HEX2, 24 HEX1,HEX0; 25 26 wire 2:0M7,M6,M5,M4,M3,M2,M1,M0; 27 28 mux_3bit_8to1 N7(SW17:15,SW2:0,SW2:0,SW2:0, SW14:12,SW11:9,SW8:6,SW8:6,SW5:3,M7); 29 30 mux_3bit_8to1 N6(SW17:15,SW2:0,SW2:0,SW14:12, SW11:9,SW8:6,SW8:6,SW5:3,SW2:0,M6); 31 32 mux_3bit_8to1 N5(SW17:15,SW2:0,SW14:12, 33 SW11:9,SW8:6,SW8:6,SW5:3,SW2:0,SW2:0,M5); 34 35 mux_3bit_8to1 N4(SW17:15,SW14:12,SW11:9, 36 SW8:6,SW8:6,SW5:3,SW2:0,SW2:0,SW2:0,M4); 37 38 mux_3bit_8to1 N3(SW17:15,SW11:9,SW8:6,SW8:6, SW5:3,SW2:0,SW2:0,SW2:0,SW14:12,M3); 39 40 mux_3bit_8to1 N2(SW17:15,SW8:6,SW8:6,SW5:3, SW2:0,SW2:0,SW2:0,SW14:12,SW11:9,M2); 41 42 mux_3bit_8to1 N1(SW17:15,SW8:6,SW5:3, 43 SW2:0,SW2:0,SW2:0,SW14:12,SW11:9,SW8:6,M1); 44 45 mux_3bit_8to1 N0(SW17:15,SW5:3,SW2:0,SW 2:0, SW2:0,SW14:12,SW11:9,SW8:6,SW8:6,M0); 46 47 char_7seg H7(M7,HEX7); 48 49 char_7seg H6(M6,HEX6); 50 51 char_7seg H5(M5,HEX5); 52 53 char_7seg H4(M4,HEX4); 54 55 char_7seg H3(M3,HEX3); 56 57 char_7seg H2(M2,HEX2); 58 59 char_7seg H1(M1,HEX1); 60 61 char_7seg H0(M0,HEX0); 62 63 endmodule 64 65 /3bit 8to1 multiplexer 66 67 /use 7 3bit 2-to-1 multiplexer 68 69 module mux_3bit_8to1(S,U,V,W,X,Y,Z,A,B,M); 70 71 input 2:0S,U,V,W,X,Y,Z,A,B; 72 73 output 2:0M; 74 75 wire 2:0n0,n1,n2,n3,n4,n5; 76 77 / 2 to 1 Multiplexers 78 79 /one 80 81 assign n00 = (S0&U0)|(S0&V0); 82 83 assign n01 = (S0&U1)|(S0&V1); 84 85 assign n02 = (S0&U2)|(S0&V2); 86 87 /two 88 89 assign n10 = (S0&W0)|(S0&X0); 90 91 assign n11 = (S0&W1)|(S0&X1); 92 93 assign n12 = (S0&W2)|(S0&X2); 94 95 /three 96 97 assign n20 = (S0&Y0)|(S0&Z0); 98 99 assign n21 = (S0&Y1)|(S0&Z1); 100 101 assign n22 = (S0&Y2)|(S0&Z2); 102 103 /four 104 105 assign n30 = (S0&A0)|(S0&B0); 106 107 assign n31 = (S0&A1)|(S0&B1); 108 109 assign n32 = (S0&A2)|(S0&B2); 110 111 /five 112 113 assign n40 = (S1&n00)|(S1&n10); 114 115 assign n41 = (S1&n01)|(S1&n11); 116 117 assign n42 = (S1&n02)|(S1&n12); 118 119 /six 120 121 assign n50 = (S1&n20)|(S