fpga电梯论文-百度文库.doc

xiyangyang423doc: FPGA VHDL,. ,3 . EDA, , , , ,. VHDL, , .EDA, ,.: :VHDL,EDA,1AbstractIntroduced based on the VHDL language design elevator controller, and has carried on the electric circuit synthesis and the simulation. This controller follows the direction first principle, provides 3 floors multiuser to carry passengers to serve and to instruct the elevator the movement situation. The EDA technology is not some discipline branch, or some kind of new of skill technology, it is a comprehensive discipline, fuses multily-disciplinary in a body, has broken barrier between the software and the hardware, causes the computer the software and the hardware realization, the rated capacity and the product performance combines, it has represented the electronic design technology and the application technology development direction. VHDL has with the concrete hardware electric circuit has nothing to do with and designs the characteristic which the platform has nothing to do with, and has the good electric circuit behavior description and the system description ability, and in language legible and has orderliness the structurization design aspect, has displayed the formidable vitality and the application potential. EDA is refers take the computer as the working platform, fused the application electronic technology, computer technology, the information processing and the intellectualized technology newest achievement, carries on the electronic products automatic to design.word: VHDL, controller, EDA, elevator Key word2 1 .1 1.1 .1 1.2 .2 2 VHDL,EDA .32.1 VHDL .3 2.2 EDA .42.3EDA.5 3 . 83.1 . 8 3.2 8 3.3 .8 3.4 , 12 3.5 . 20 4 4.1 . 4.2 4.3 8 7 () .32 .33 33311.1 EDA(Electronic Desion Automation) "" , , . , VHDL,VerilogHDL ., ,. EDA , EDA , HDL(Hardware Description Language) ,( ) ,.EDA , EDA . EDA ,IC ,ASIC ,FPGA/CPLD ,;(CAD) , (CAM) ,(CAT) ,(CAE) ; , . EDA .EDA , , , . EDA , ASIC , ASIC , EDA . VHDL(Very High Speed Integrated Circuit Hardware Description Language) , .VHDL , ; VHDL 4,.VHDL , , .VHDL , , ,.VHDL , , ,. VHDL ,. VHDL , . FPGA .1.2 ,. ,., , , .:( ),FPGA/CPLD ,. , . , , ,. FPGA/CPLD , , . , , . , , 5, , ,., . .FPGA/CPLD , , ,. FPGA/CPLD . FPGA/CPLD ,. . 90 FPGA/CPLD , FPGA/CPLD ., FPGA/CPLD . . , ., FPGA/CPLD ,. FPGA(Fiela Programmable Gates Array,) CPLD (Cornplex Programmable Logic Device ,) , PAL,GAL . PAL, GAL.,FPGA/CPLD , , IC . FPGA/CPLD . . ,ROM , PROM EPROM , , EPROM ,.FPGA , . , , FPGA/CPLD 6. , ,. ,. ,.7VHDL,EDA 2 VHDL,EDAVHDL80,"(VHSIC Hardware Description Language), VHDLDA, ,19863,IEEVHDL ,VHDL.198712,IEEEIEEE Std1076-1987. VHDLIEE,. 1995, CAD VHDL , (EDA).VHDL ,IEEE,IEEE Std 1076-1987.19934(ANSI) .9IEEE,IEEE Std 1076-1993.VHDL , .VHDL. ,VHDLVerilogIEE,EDA, .VHDL 2.1 VHDLVHDL, ,VHDL . VHDL ,. ., ,., , . VHDL, .,VHDL 1., ;,; 2. , (Botom-up) , 8(Top-down);, ; ; 3.,;,; 4., ; 5.,;VHDL ,; 6.,: 7., ,. 8. VHDL; 9. VHDL, , , .EDA 2.2 EDAEDA(Electronic Design Automatic)CAD (Computer Aided Design), , . EDA, (IC:Integrated Circuits)(PCB: PrintedCircuit Board) .,. ,EDA. EDA,EDA . EDA,1995 , ,EDA. EDA, , 50%.IVY.9PCASIC,(11%) ., EDA,.2.3EDA 2.3EDA EDA,(DSI) (IC), , , , , ,., , ; , (Electronic DesignAutomation-EDA) . (EDA)(CAD/CAM) ., , , , . EDA, VHDL, (top-down), .,: (l), ., . (2), ,. (3), ,10, . (4)IEEE 1076VHDL, ,. (5),EDA: ,. ,.C 2-2EDA2-2EDAEDA , ,(PCB)() , .1-111EDA.,EDA , ., , , . ,. .,. , .DSP,C,PCB , ASIC FPGAIEPLDEDACadence Design System Inc. ,Mentor Graphics Inc.,SynopsysInc,Dazix-Intergraph Inc.12 3 3.1 VHDL , , .3.2 (1), . (2)(). (3)(). (4), 1s , 4s ,() , . (5), . (6):, , ,. ,. (7).3.3 1 , ,., ,. . ,. ,.13 1 VHDL ,: library ieee use ieee std_loigic_unsigned.all entity ladder 3 is porl(clk,switch,close,delay:std_logic; /, dir: in std_logic_vector(2 down to 0); /up lift,down lift : in std_logic_vector(3 down to 0); /, qout : out std_logic_vector(3 down to 0); lamp : out std_logic_vector(1 down to 0); end ladder 3 3 , . urr(3b ) ,drr(3b ) ,ur(),dr( ) ,let() , qout, lamp lift,ladd, time. / /14. , ladd "01", urr ., time "110" . urr . drr . urr drr ur dr . . 3 wait, upper, down. 2Switch=1Wait()ur=1 ur=0,dr=0 ur=0,dr=0 ur =1Upper()dr=1 ur=1 2 Down() switch "0", ladd "00" . Switch "