EDA(中国地质大学 )课堂作业.doc

1题：4选1生成8个library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity ff isport(ain:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic );end ;architecture bhv of ff isbegin y=ain(conv_integer(sel);end bhv;library ieee;use ieee.std_logic_1164.all;package newtype istype ary84 is array (7 downto 0,3 downto 0) of std_logic;type ary82 is array (7 downto 0,1 downto 0) of std_logic;End package;library ieee;use ieee.std_logic_1164.all;use work.newtype.all;entity f isport(ain84:in ary84; sel84:in ary82; y84:out std_logic_vector(7 downto 0); count:out std_logic);end ;architecture t of f iscomponent ff isport(ain:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic );end component;signal y841: std_logic_vector(7 downto 0);begin gen1:for n in 0 to 7 generateux: ff port map(ain84(n,3)&ain84(n,2)&ain84(n,1)&ain84(n,0),sel84(n,1)&sel84(n,0),y841(n);end generate;y84=y841;process(y841)variable tmp:std_logic;begintmp:=1;for i in 0 to 7 looptmp:=tmp and y841(i);end loop;count=tmp;end process;end architecture; 2题：5-4状态机library ieee;use ieee.std_logic_1164.all;entity ff isport(clk,res:in std_logic;ina:in std_logic_vector(0 to 2);outa:out std_logic_vector(3 downto 0);end ff;architecture f1 of ff istype sta is(s0,s1,s2,s3);signal cs,ns:sta;beginreg:process(clk,res) begin if res=1 then cs=s0; elsif clkevent and clk=1 then cs ns=s1; if ina=101 then outa=0010; elsif ina=111 then outa outa=1001; if ina=000 then ns=s1; elsif ina=110 then ns=s2;else ns outa=1111; if ina=011 then ns=s1; elsif ina=100 then ns=s2; else ns ns=s0; if ina=101 then outa=1101; elsif ina=011 then outa=1110; end if; end case; end process; end architecture;3题：例题5-2library ieee;use ieee.std_logic_1164.all;entity ff isport(clk,res:in std_logic;ina:in std_logic_vector(0 to 2);outa:out std_logic_vector(3 downto 0);end ff;architecture f1 of ff istype sta is(s0,s1,s2,s3);signal cs,ns:sta;beginreg:process(clk,res) begin if res=1 then cs=s0; elsif clkevent and clk=1 then cs ns=s1; if ina=101 then outa=0010; elsif ina=111 then outa outa=1001; if ina=000 then ns=s1; elsif ina=110 then ns=s2;else ns outa=1111; if ina=011 then ns=s1; elsif ina=100 then ns=s2; else ns ns=s0; if ina=101 then outa=1101; elsif ina=011 then outa=1110; end if; end case; end process; end architecture;4题library ieee;use ieee.std_logic_1164.all;entity ff isport(clk:in std_logic; q1,q2:out std_logic);end entity;architecture f1 of ff isprocedure dd (signal clk1:in std_logic;- signal q:inout std_logic) is begin if clk1event and clk1=1 then q=not q;end if; return ; end dd;signal qs1,qs2:std_logic;beginprocess(clk)begindd(clk,qs1);dd(qs1,qs2);end process;q1=qs1;q2 cin cin cin cin cin cin cin cin cin cin cin=1111111;END CASE;END PROCESS;END ARCHITECTURE;7题例题7-4奇偶校验位LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ff IS PORT(a:in STD_LOGIC_VECTOR(7 DOWNTO 0); y:OUT STD_LOGIC);END ENTITY;ARCHITECTURE f OF ff ISBEGINPROCESS(a)variable tmp:STD_LOGIC:=0;BEGINfor n in 0 to 7 looptmp:=tmp xor a(n);end loop;y cin cin cin cin null;end case;end process;end architecture;9、题一位二进制全减器 习题341位二进制全减器顶层设计描述library ieee;use ieee.std_logic_1164.all;entity f_m isport (x,y,subin:in std_logic;diffr,subout:out std_logic);end entity f_m;architecture fd1 of f_m iscomponent h_mport (x,y:in std_logic;diff,sout:out std_logic);end component;signal d,e,f:std_logic;beginu1:h_m port map(x,y,d,e);u2:h_m port map(d,subin,diffr,f);subout=e or f;end;半减器描述，布尔方程描述法，及或门逻辑描述library ieee;use ieee.std_logic_1164.all;entity h_m isport (x,y:in std_logic;diff,sout:out std_logic);end entity h_m;architecture fh1 of h_m isbeginsout=(not x) and y;diff=x xor y;end architecture fh1;10、二选一多路选择器：library ieee;use ieee.std_logic_1164.all;entity mux21 isport(a,b,s:in std_logic;y:out std_logic);end entity;architecture one of mux21 isbeginy = a when s=0 else b;end architecture one;11.四选一电路library ieee;use ieee.std_logic_1164.all;entity x4 is port ( a,b,c,d,s0,s1:in std_logic; y:out std_logic);end;architecture bhv of x4 issignal q:std_logic_vector(1 downto 0); begin q y y y y=d; end case; end process;end; 3（本题8分）信号赋值语句在什么情况下做并行语句？在什么情况下做顺序语句？信号赋值符号和变量赋值符号分别是什么？两种赋值符号有什么区别？ 【参考答案】： 信号赋值语句在进程外做并行语句，并发执行，与语句所处的位值无关。2分信号赋值语句在进程内或子程序内做顺序语句，按顺序执行，与语句所处的位值有关。2分信号赋值符号为“=”。1分变量赋值符号为“:=”。1分信号赋值符号用于信号赋值动作，不立即生效。1分变量赋值符号用于变量赋值动作，立即生效。1分 1（本题9分）门电路是构成组合逻辑电路的基本单元。基本门电路主要包括非门、与门、与非门、或门、或非门、异或门、同或门等。请用VHDL设计一个四输入与非门。【参考答案】： LIBRARY IEEE ； USE IEEE.STD_LOGIC_1164.ALL ； -2分ENTITY test1 IS -3分 PORT(A, B, C, D : IN STD_LOGIC ； Q : OUT STD_LOGIC ) ； END test1 ； ARCHITECTURE test1 OF test1 IS -2分BEGIN Q = not（A and B and C and D）； -2分END test1 ； 2 （本题12分）优先级编码器常用于中断的优先级控制。请用VHDL设计一个8位输入，3位编码输出的优先级编码器。该编码器的真值表如下所示（表中“x”表示任意值，“Z”表示高阻态）。3 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; -2分ENTITY test2 IS -3分PORT(input : IN STD_LOGIC_VECTOR(7 DOWNTO 0); y : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); END test2; ARCHITECTURE test2 OF test2 IS -2分BEGIN PROCESS (input) -1分BEGIN IF(input(0) = 0)THEN -2分y=000; ELSI