并串转换设计源程序.doc

1、 常用经典电路设计S2P输入串行数据流信息：/*/ description / S2P/*Module s2p (rst_n, clk, sdata_in, pdata_out ) ;Input rst_n, clk ;Input sdata_in ;Output reg 7:0 pdata_out ; reg 2:0 count ;always (posedge clk or negedge rst_n) begin if (rst_n) count = 3h00 ; else count = count + 1b1 ; endreg div8_clk ;always (posedge clk or negedge rst_n) begin if (rst_n) div8_clk = 1h0 ; else if (count=3h3) div8_clk = 1b1 ;else if (count=3h7) div8_clk = 1b0 ; end/ assign div8_clk = (count=3h4) | (count=3h5)| (count=3h6)| (count=3h7) ;/ assign div8_clk = (count=3h0) | (count=3h1)| (count=3h2)| (count=3h3) ;/ assign div8_clk = count2 ;reg 7:0 shift_data ;always (posedge clk or negedge rst_n) begin if (rst_n) shift_data = 8h00 ; else shift_data = shift_data6:0 , sdata_in ; endalways (posedge clk or negedge rst_n) begin if (rst_n) pdata_out = 8h00 ; else if (count=3h0) pdata_out = shift_data ; endEndmodule2、 常用经典电路设计P2S/*/ description / P2S/*/*/ description / P2S/*Module p2s (rst_n, clk, div8_clk, pdata_in, sdata_out ) ;Input rst_n, clk, div8_clk ;Input 7:0 pdata_in ;Output sdata_out ; reg 2:0 count ;always (posedge clk or negedge rst_n) begin if (rst_n) count = 3h00 ; else count = count + 1b1 ; endreg div8_clk ;always (posedge clk or negedge rst_n) begin if (rst_n) div8_clk = 1h0 ; else if (count=3h3) div8_clk = 1b1 ;else if (count=3h7) div8_clk = 1b0 ; end/ assign div8_clk = (count=3h4) | (count=3h5)| (count=3h6)| (count=3h7) ;/ assign div8_clk = (count=3h0) | (count=3h1)| (count=3h2)| (count=3h3) ;/ assign div8_clk = count2 ;reg 7:0 shift_data ;always (posedge clk or negedge rst_n) begin if (rst_n) pdata_out = 8h00 ; else if (count=3h0) pdata_out = pdata_i