PLD符号元件说明.doc

在PLD Symbols.lib库中有多达360种的PLD库元件。1. 运算器ACC1：1-Bit loadable cascadable accumulator with carry-in, carry-out, and synchronous reset。ACC16：16-Bit loadable cascadable accumulator with carry-in, carry-out, and synchronous reset。ACC4：4-Bit loadable cascadable accumulator with carry-in, carry-out, and synchronous reset。ACC8：8-Bit loadable cascadable accumulator with carry-in, carry-out, and synchronous reset。ADD1：1-Bit full adder with carry-in and carry-out。ADD16：16-Bit full adder with carry-in and carry-out。ADD4：4-Bit full adder with carry-in and carry-out。ADD8：8-Bit full adder with carry-in and carry-out。ADSU1：1-Bit cascadable adder/subtractor with carry-in and carry-out。ADSU16：16-Bit cascadable adder/subtractor with carry-in and carry-out。ADSU4：4-Bit cascadable adder/subtractor with carry-in and carry-out。ADSU8：8-Bit cascadable adder/subtractor with carry-in, carry-out and Overflow。X74_280：9-Bit Odd/Even Parity generator/checker。X74_283：4-Bit full adder with carry-in and carry-out。2. 缓冲器BUF：General purpose buffers。BUF16：General purpose buffers。BUF4：General purpose buffers。BUF8：General purpose buffers。BUFE：Internal 3-State buffers。BUFE16：Internal 3-State buffers。BUFE4：Internal 3-State buffers。BUFE8：Internal 3-State buffers。BUFG：Global clock buffer。BUFGP：Primary Global buffer for driving clocks or long lines (Four per PLD device)。BUFGS：Secondary buffer for driving clocks or long lines (Four per PLD device)。BUFT：Internal 3-State buffers。BUFT16：Internal 3-State buffers。BUFT4：Internal 3-State buffers。BUFT8：Internal 3-State buffers。3. 比较器COMP16：16-Bit Identity Comparator。COMP2：2-Bit Identity Comparator。COMP4：4-Bit Identity Comparator。COMP8：8-Bit Identity Comparator。COMPM16：16-Bit Magnitude Comparator。COMPM2：2-Bit Magnitude Comparator。COMPM4：4-Bit Magnitude Comparator。COMPM8：8-Bit Magnitude Comparator。COMPMC16：16-Bit Magnitude Comparator。COMPMC8：8-Bit Magnitude Comparator。X74_518：8-Bit identity comparator with active-low enable。X74_521：8-Bit identity comparator with active-low enable and output。X74_L85：4-Bit expandable magnitude comparator。4. 计数器CB16CE：16-Bit cascadable binary counter with clock enable and asynchronous Clear。CB16CLE：16-Bit loadable cascadable binary counter with clock enable and asynchronous Clear。CB16CLED：16-Bit loadable cascadable bi-directional binary counter with clock enable and asynchronous Clear。CB16RE：16-Bit cascadable binary counter with clock enable and synchronous reset。CB2CE：2-Bit cascadable binary counter with clock enable and asynchronous Clear。CB2CLE：2-Bit loadable cascadable binary counter with clock enable and asynchronous Clear。CB2CLED：2-Bit loadable cascadable bi-directional binary counter with clock enable and asynchronous Clear。CB2RE：2-Bit cascadable binary counter with clock enable and synchronous reset。CB4CE：4-Bit cascadable binary counter with clock enable and asynchronous Clear。CB4CLE：4-Bit loadable cascadable binary counter with clock enable and asynchronous Clear。CB4CLED：4-Bit loadable cascadable bi-directional binary counter with clock enable and asynchronous Clear。CB4RE：4-Bit cascadable binary counter with clock enable and synchronous reset。CB8CE：8-Bit cascadable binary counter with clock enable and asynchronous Clear。CB8CLE：8-Bit loadable cascadable binary counter with clock enable and asynchronous Clear。CB8CLED：8-Bit loadable cascadable bi-directional binary counter with clock enable and asynchronous Clear。CB8RE：8-Bit cascadable binary counter with clock enable and synchronous reset。CC16CE：16-Bit cascadable binary counter with clock enable and asynchronous Clear。CC16CLE：16-Bit loadable cascadable binary counter with clock enable and asynchronous Clear。CC16CLED：16-Bit loadable cascadable bidirectional binary counter with clock enable and asynchronous Clear。CC16RE：16-Bit cascadable binary counter with clock enable and synchronous reset。CC8CE：8-Bit cascadable binary counter with clock enable and asynchronous Clear。CC8CLE：8-Bit loadable cascadable binary counter with clock enable and asynchronous Clear。CC8CLED：8-Bit loadable cascadable bidirectional binary counter with clock enable and asynchronous Clear。CC8RE：8-Bit cascadable binary counter with clock enable and synchronous reset。CD4CE：4-Bit cascadable BCD counter with clock enable and asynchronous Clear。CD4CLE：4-Bit loadable cascadable BCD counter with clock enable and asynchronous Clear。CD4RE：4-Bit cascadable BCD counter with clock enable and synchronous reset。CD4RLE：4-Bit loadable cascadable BCD counter with clock enable and synchronous reset。CJ4CE：4-Bit Johnson counter with clock enable and asynchronous Clear。CJ4RE：4-Bit Johnson counter with clock enable and synchronous reset。CJ5CE：5-Bit Johnson counter with clock enable and asynchronous Clear。CJ5RE：5-Bit Johnson counter with clock enable and synchronous reset。CJ8CE：8-Bit Johnson counter with clock enable and asynchronous Clear。CJ8RE：8-Bit Johnson counter with clock enable and synchronous reset。CR16CE：16-Bit Negative-Edge binary ripple counter with clock enable and asynchronous Clear。CR8CE：8-Bit Negative-Edge binary ripple counter with clock enable and asynchronous Clear。X74_160：4-Bit BCD counter with parallel and trickle enables, active-low load enable and synchronous reset。X74_161：4-Bit binary counter with parallel and trickle enables, active-low load enable and synchronous reset。X74_162：4-Bit binary counter with parallel and trickle enables, active-low load enable and synchronous reset。X74_163：4-Bit binary counter with parallel and trickle enables, active-low load enable and synchronous reset。X74_168：4-Bit BCD bi-directional counter with parallel and trickle clock enables and active-low load enable。X74_390：4-Bit BCD/Bi-Quinary counter with negative-edge clock and asynchronous clear。5. 数据寄存器X74_174：6-Bit Data register with active-low asynchronous clear。X74_273：8-Bit Data register with active-low asynchronous clear。X74_377：8-Bit Data register with active-low clock enable。6. 译码器D2_4E：2-to-4 Decode/Demultiplexer with enable。D3_8E：3-to-8 Decode/Demultiplexer with enable。D4_16E：4-to-16 Decode/Demultiplexer with enable。X74_42：4-line to 10-line BCD-to-Decimal decode with active-low outputs。X74_138：3-to-8 line decoder/demultiplexer with active-low outputs and three enables。X74_139：2-to-4 line decoder/demultiplexer with active-low outputs and active-low enable。X74_154：4-to-16 line decoder/demultiplexer with active-low outputs and two enables。7. 编码器X74_147：10-to-4 line priority encoder with active-low inputs and outputs。X74_148：8-to-3 line cascadable priority encoder with active-low inputs and outputs。8. 触发器FD：D Flip-Flop。FD_1：D Flip-Flop with negative-edge clock。FD16CE：16-Bit data register with clock enable and asynchronous clear。FD16RE：16-Bit data register with clock enable and synchronous reset。FD4CE：4-Bit data register with clock enable and asynchronous clear。FD4RE：4-Bit data register with clock enable and synchronous reset。FD8CE：8-Bit data register with clock enable and asynchronous clear。FD8RE：8-Bit data register with clock enable and synchronous reset。FDC：D Flip-Flop with asynchronous clear。FDC_1：D Flip-Flop with negative-edge clock and asynchronous clear。FDCE：D Flip-Flop with clock enable and asynchronous clear。FDCE_1：D Flip-Flop with negative-edge clock, clock enable and asynchronous clear。FDCP：D Flip-Flop with asynchronous preset and clear。FDCPE：D Flip-Flop with clock enable and asynchronous preset and clear。FDCS：D Flip-Flop with asynchronous set and clear。FDP：D Flip-Flop with asynchronous preset。FDP_1：D Flip-Flop with negative-edge clock and asynchronous preset。FDPE：D Flip-Flop with clock enable and asynchronous preset。FDPE_1：D Flip-Flop with negative-edge clock, clock enable and asynchronous preset。FDR：D Flip-Flop with synchronous reset。FDRE：D Flip-Flop with clock enable and synchronous reset。FDRS：D Flip-Flop with synchronous reset and synchronous set。FDRSE：D Flip-Flop with synchronous reset and set and clock enable。FDS：D Flip-Flop with synchronous set。FDSE：D Flip-Flop with clock enable and synchronous set。FDSR：D Flip-Flop with synchronous set and synchronous reset。FDSRE：D Flip-Flop with synchronous set and reset and clock enable。FJKC：J-K Flip-Flop with asynchronous clear。FJKCE：J-K Flip-Flop with clock enable and asynchronous clear。FJKCP：J-K Flip-Flop with asynchronous clear and preset。FJKCPE：J-K Flip-Flop with clock enable and asynchronous clear and preset。FJKCS：J-K Flip-Flop with asynchronous clear and set。FJKP：J-K Flip-Flop with asynchronous preset。FJKPE：J-K Flip-Flop with clock enable and asynchronous preset。FJKRSE：J-K Flip-Flop with clock enable and synchronous reset and set。FJKSRE：J-K Flip-Flop with clock enable and synchronous reset and set。FTC：Toggle Flip-Flop with toggle enable and asynchronous clear。FTCE：Toggle Flip-Flop with toggle enable, clock enable and asynchronous clear。FTCLE：Toggle/loadable Flip-Flop with toggle enable, clock enable and asynchronous clear。FTCP：Toggle Flip-Flop with toggle enable and asynchronous clear and preset。FTCPE：Toggle Flip-Flop with toggle enable, clock enable and asynchronous clear and preset。FTCPLE：Toggle/loadable Flip-Flop with toggle enable, clock enable and asynchronous clear and preset。FTCS：Toggle Flip-Flop with toggle enable and asynchronous clear and set。FTP：Toggle Flip-Flop with toggle enable and asynchronous preset。FTPE：Toggle Flip-Flop with toggle enable, clock enable and asynchronous preset。FTPLE：Toggle/loadable Flip-Flop with toggle enable, clock enable and asynchronous preset。FTRSE：Toggle Flip-Flop with toggle enable, clock enable and synchronous reset and set。FTRSLE：Toggle/loadable Flip-Flop with toggle enable, clock enable and synchronous reset and set。FTSRE：Toggle Flip-Flop with toggle enable, clock enable and synchronous reset and set。FTSRLE：Toggle/loadable Flip-Flop with toggle enable, clock enable and synchronous reset and set。9. 输入/输出触发器IFD：Input D Flip-Flop。IFD_1：Input D Flip-Flop with inverted clock。IFD16：16 x Input D Flip-Flops。IFD4：4 x Input D Flip-Flops。IFD8：8 x Input D Flip-Flops。OFD：Output D Flip-Flop。OFD_1：Output D Flip-Flop with inverted clock。OFD16：16 x Output D Flip-Flop。OFD4：4 x Output D Flip-Flop。OFD8：8 x Output D Flip-Flop。OFDE：Output D Flip-Flop with active-high enable output buffer。OFDE_1：Output D Flip-Flop with active-high enable output buffer and inverted clock。OFDE16：16 x Output D Flip-Flop with active-high enable output buffer。OFDE4：4 x Output D Flip-Flop with active-high enable output buffer。OFDE8：8 x Output D Flip-Flop with active-high enable output buffer。OFDT：Output D Flip-Flop with active-high 3-state and active-low enable output buffer。OFDT_1：Output D Flip-Flop with active-high 3-state and active-low enable output buffer and inverted clock。OFDT16：16 x Output D Flip-Flop with active-high 3-state and active-low enable output buffer。OFDT4：4 x Output D Flip-Flop with active-high 3-state and active-low enable output buffer。OFDT8：8 x Output D Flip-Flop with active-high 3-state and active-low enable output buffer。10. 输入/输出缓冲器IBUF：Input buffer。IBUF16：16 x Input buffers。IBUF4：4 x Input buffers。IBUF8：8 x Input buffers。OBUF：Output buffer。OBUF16：16 x Output buffer。OBUF4：4 x Output buffer。OBUF8：8 x Output buffer。OBUFE：3-state Output buffer with active-high output enable。OBUFE16：16 x 3-state Output buffer with active-high output enable。OBUFE4：4 x 3-state Output buffer with active-high output enable。OBUFE8：8 x 3-state Output buffer with active-high output enable。OBUFT：3-state Output buffer with active-low output enable。OBUFT16：16 x 3-state Output buffer with active-low output enable。OBUFT4：4 x 3-state Output buffer with active-low output enable。OBUFT8：8 x 3-state Output buffer with active-low output enable。11. 输入/输出端口IOPAD：Input/Output Pad。IOPAD16：16 x Input Pads。IOPAD4：4 x Input/Output Pads。IOPAD8：8 x Input/Output Pads。IPAD：Input Pad。IPAD16：16 x Input Pads。IPAD4：4 x Input Pads。IPAD8：8 x Input Pads。OPAD：Output Pad。OPAD16：16 x Output Pads。OPAD4：4 x Output Pads。OPAD8：8 x Output Pads。12. 输入锁存器ILD：Input transparent Data Latch。ILD_1：Input transparent Data Latch with inverted gate。ILD16：16 x Input Transparent Data Latches。ILD4：4 x Input Transparent Data Latches。ILD8：8 x Input Transparent Data Latches。13. 反相器INV：Inverter。INV16：16 x Inverters。INV4：4 x Inverters。INV8：8 x Inverters。14. 锁存器LD：Transparent Data Latch。LD_1：Transparent Data Latch with inverted gate。LD16：16 x Transparent Data Latch。LD4：4 x Transparent Data Latch。LD8：8 x Transparent Data Latch。15. 与门和与非门AND2：2-Input and gate。AND2B1：2-Input and gate with one input inverted。AND2B2：2-Input and gate with two inputs inverted。AND3：3-Input AND gate。AND3B1：3-Input AND gate with one input inverted。AND3B2：3-Input AND gate with two inputs inverted。AND3B3：3-Input AND gate with three inputs inverted。AND4：4-Input AND gate。AND4B1：4-Input AND gate with one input inverted。AND4B2：4-Input AND gate with two inputs inverted。AND4B3：4-Input AND gate with three inputs inverted。AND4B4：4-Input AND gate with four inputs inverted。AND5：5-Input AND gate。AND5B1：5-Input AND gate with one input inverted。AND5B2：5-Input AND gate with two inputs inverted。AND5B3：5-Input AND gate with three inputs inverted。AND5B4：5-Input AND gate with four inputs inverted。AND5B5：5-Input AND gate with five inputs inverted。AND6：6-Input AND gate。AND7：7-Input AND gate。AND8：8-Input AND gate。AND9：9-Input AND gate。NAND2：2-Input NAND gate。NAND2B1：2-Input NAND gate with one input inverted。NAND2B2：2-Input NAND gate with two inputs inverted。NAND3：3-Input NAND gate。NAND3B1：3-Input NAND gate with one input inverted。NAND3B2：3-Input NAND gate with two inputs inverted。NAND3B3：3-Input NAND gate with three inputs inverted。NAND4：4-Input NAND gate。NAND4B1：4-Input NAND gate with one input inverted。NAND4B2：4-Input NAND gate with two inputs inverted。NAND4B3：4-Input NAND gate with three inputs inverted。NAND4B4：4-Input NAND gate with four inputs inverted。NAND5：5-Input NAND gate。NAND5B1：5-Input NAND gate with one input inverted。NAND5B2：5-Input NAND gate with two inputs inverted。NAND5B3：5-Input NAND gate with three inputs inverted。NAND5B4：5-Input NAND gate with four inputs inverted。NAND5B5：5-Input NAND gate with five inputs inverted。NAND6：6-Input NAND gate。NAND7：7-Input NAND gate。NAND8：8-Input NAND gate。NAND9：9-Input NAND gate。16. 或门和或非门NOR2：2-Input NOR gate。NOR2B1：2-Input NOR gate with one input inverted。NOR2B2：2-Input NOR gate with two inputs inverted。NOR3：3-Input NOR gate。NOR3B1：3-Input NOR gate with one input inverted。NOR3B2：3-Input NOR gate with two inputs inverted。NOR3B3：3-Input NOR gate with three inputs inverted。NOR4：4-Input NOR gate。NOR4B1：4-Input NOR gate with one input inverted。NOR4B2：4-Input NOR gate with two inputs inverted。NOR4B3：4-Input NOR gate with three inputs inverted。NOR4B4：4-Input NOR gate with four inputs inverted。NOR5：5-Input NOR gate。NOR5B1：5-Input NOR gate with one input inverted。NOR5B2：5-Input NOR gate with two inputs inverted。NOR5B3：5-Input NOR gate with three inputs inverted。NOR5B4：5-Input NOR gate with four inputs inverted。NOR5B5：5-Input NOR gate with five inputs inverted。NOR6：6-Input NOR gate。NOR7：7-Input NOR gate。NOR8：8-Input NOR gate。NOR9：9-Input NOR gate。OR2：2-Input OR gate。OR2B1：2-Input OR gate with one input inverted。OR2B2：2-Input OR gate with two inputs inverted。OR3：3-Input OR gate。OR3B1：3-Input OR gate with one input inverted。OR3B2：3-Input OR gate with two inputs inverted。OR3B3：3-Input OR gate with three inputs inverted。OR4：4-Input OR gate。OR4B1：4-Input OR gate with one input inverted。OR4B2：4-Input OR gate with two inputs inverted。OR4B3：4-Input OR gate with three inputs inverted。OR4B4：4-Input OR gate with four inputs inverted。OR5：5-Input OR gate。OR5B1：5-Input OR gate with one input inverted。OR5B2：5-Input OR gate with two inputs inverted。OR5B3：5-Input OR gate with three inputs inverted。OR5B4：5-Input OR gate with four inputs inverted。OR5B5：5-Input OR gate with five inputs inverted。OR6：6-Input OR gate。OR7：7-Input OR gate。OR8：8-Input OR gate。OR9：9-Input OR gate。17. 同门和异门SOP3：3-Input sum-of-products function。SOP3B1A：3-Input sum-of-products with one AND input inverted。SOP3B1B：3-Input sum-of-products function with one OR input inverted。SOP3B2A：3-Input sum-of-products with two AND inputs inverted。SOP3B2B：3-Input sum-of-products function with one OR and one AND input inverted。SOP3B3：3-Input sum-of-products function with all inputs inverted。SOP4：4-Input sum-of-products function。SOP4B1：4-Input sum-of-products with one AND input inverted。SOP4B2A：4-Input sum-of-products function with both inputs on one AND gate inverted。SOP4B2B：4-Input sum-of-products with one AND input on each AND gate inverted。SOP4B3：4-Input sum-of-products function with three inputs inverted。SOP4B4：4-Input sum-of-products function with all inputs inverted。XNOR2：2-input XNOR Gates with non-inverted inputs。XNOR3：3-input XNOR Gates with non-inverted inputs。XNOR4：4-input XNOR Gates with non-inverted inputs。XNOR5：5-input XNOR Gates with non-inverted inputs。XNOR6：6-input XNOR Gates with non-inverted inputs。XNOR7：7-input XNOR Gates with non-inverted inputs。XNOR8：8-input XNOR Gates with non-inverted inputs。XNOR9：9-input XNOR Gates with non-inverted inputs。XOR2：2-input XOR Gates with non-inverted inputs。XOR3：3-input XOR Gates with non-inverted inputs。XOR4：4-input XOR Gates with non-inverted inputs。XOR5：5-input XOR Gates with non-inverted inputs。XOR6：6-input XOR Gates with non-inverted inputs。XOR7：