FPGA设计实践课程设计报告打铃系统.doc

上海电力学院课程设计报告课程设计名称： FPGA设计实践课程设计 设计课题名称： 自动打铃系统 班级： 2007142 指导老师： 赵倩 姓名： 徐晓敏 学号： 20072702 成绩： 设计时间： 2010.7.5.2010.7.8 设计地点： 实验室303 计算机信息与工程学院 自动打铃系统报告一、 设计目的：使用Quartus II完成自动打铃系统的设计二、 实验器材和工具软件：Pc机使用Quartus II系统De2平台三、 设计内容：1. 基本计时和现实功能（用12小时制显示）：包括上下午标志，时、分的数字显示，秒信号显示。2. 可以自由设置当前时间（包含上、下午，时、分）。3. 可以实现基本的打铃功能，规定： 上午06：00起床铃，打铃5s，停2s，再打铃5s； 下午10：30熄灯铃，打铃5s，停2s，再打铃5s。 铃声可以用LED灯光显示，如果实验装置没有LED发光管，那么可以用七段显示管的小数点显示，也可以用显示小时的十位数码管的多余段显示。凡是用到铃声功能的均可以如此处理。 4. 增加整点报时功能，整点时响铃5s。要求有控制启动和关闭功能。5. 增加调整起床铃、熄灯铃时间的功能。 6. 增加调整打铃时间长短和间隙时间长短的功能。 7. 增设上午4节课的上、下课打铃功能，规定： 7：30上课，8：20下课 8：30上课，9：20下课 9：40上课，10：30下课 10：40上课，11：30下课。 每次铃响5s。 四、 设计具体步骤：1、 完成各个模块的设计，其具体代码如下：module clock (clock, en, adjusth, adjustm, adjusts, adjustpm, second, minute, hour);input clock;input en;input adjusth;input adjustm;input adjusts;input adjustpm;output4:0 hour;reg4:0 hour;output5:0 minute;reg5:0 minute;output5:0 second;reg5:0 second;always (posedge clock)beginif (en = 1b1) begin if (adjustpm = 1b0) begin if (hour 12) begin hour = hour + 12 ; end else begin hour = hour - 12 ; end end else if (adjusth = 1b1) begin if (hour = 23) begin hour = 0 ; end else begin hour = hour + 1 ; end end else if (adjustm = 1b1) begin if (minute = 59) begin minute = 0 ; end else begin minute = minute + 1 ; end end else if (adjusts = 1b1) begin second = 0 ; end endelse begin if (second = 59) begin second = 0 ; if (minute = 59) begin minute = 0 ; if (hour = 23) begin hour = 0 ; end else begin hour = hour + 1 ; end end else begin minute =minute + 1 ; end end else begin second = second + 1 ; end endendendmodulemodule statemachine (clock, changemode, adjposition, adjval, command, adjbotton, flash);input clock;input changemode;input adjposition;input adjval;output 4:0 command;reg4:0 command;output2:0 adjbotton;reg2:0 adjbotton; output2:0 flash;reg2:0 flash;parameter2:0 timer = 0;parameter2:0 adj_timer = 1;parameter2:0 adj_morningtime = 2;parameter2:0 adj_eveningtime= 3;parameter2:0 adj_ringlength = 4;parameter2:0 adj_12or24 = 5;reg2:0 state;reg1:0 pos;always (posedge clock) /mo kuai 1 gong neng shi tong guo changemode de an xia lai gai bian zhuang taibegincase (state) /case state timer : /timer 0 shi beginif (changemode = 1b0) /beginstate = adj_timer ;endendadj_timer :beginif (changemode = 1b0)beginstate = adj_morningtime ;endendadj_morningtime :beginif (changemode = 1b0)beginstate = adj_eveningtime ;endendadj_eveningtime :beginif (changemode = 1b0)beginstate = adj_ringlength ;endendadj_ringlength :beginif (changemode = 1b0)beginstate = adj_12or24 ;endendadj_12or24 :beginif (changemode = 1b0)beginstate = timer ;endenddefault :beginstate = timer ;endendcaseendalways (posedge clock) /mo kuai 2begincase (state)timer : /zheng chang ji shi shibegin / command = 5b00000 ; /shu chu command wei 00000pos = 0 ; /pos wei 0endadj_timer : /tiao zheng shi jian shibeginif (command = 5b00000) /ru guo dang qian wei zheng chang ji shi zhuang taibegin/command=5b00001;pos = 1 ; / pos wei 1endelsebegin /ru guo bu shi zheng chang ji shi zhuang taiif (adjposition = 1b0) /erqie ci shi adiposition wei 1beginif (pos = 3) /erqie pos wei 3beginpos = 1 ; /pos wei 1endelsebegin /pos bu wei3 de hua pos =pos +1pos = pos + 1 ;endendendcommand = 5b00001 ; /zuo wan shang mian zhi hou command wei 00001endadj_morningtime : /tiao zheng qi chuang shi jian zhuang taibeginif (command = 5b00001) /ruguo dang qian wei tiao zheng shi jian zhuang taibeginpos = 1 ; /pos wei 1endelsebeginif (adjposition = 1b0) /fou zhe ru guo adjposition wei 1 beginif (pos = 1) /erqie pos wei 1beginpos = 2 ; /pos wei 2endelsebeginpos = 1 ; /fou ze pos bu wei 1 shi pos wei 1endendendcommand = 5b00010 ;/ zuo wan zhi hou command shu chu wei 00010 tiao zheng xi deng zhuang taiendadj_eveningtime :beginif (command = 5b00010) / tiao wan shang shi jian de zhuang tai dang command wei 00010 shibeginpos = 1 ; /pos wei 1endelsebeginif (adjposition = 1b0) /command bu wei 00010 shi adjposition wei 1 shibeginif (pos = 1) /ru guo pos wei 1beginpos = 2 ; /pos wei2endelsebeginpos = 1 ; /fou ze wei 1endendendcommand = 5b00100 ; /zhi hou command shu chu wei 00100endadj_ringlength : /tiao zheng xiang liang zhuang tai beginif (command = 5b00100) /ru guo command wei 00100beginpos = 1 ; /pos wei1endelsebeginif (adjposition = 1b0) /fou ze ru guo command bu shi 00100 qie adjposition wei 1beginif (pos = 1) /qie pos wei 1beginpos = 3 ; /pos wei 3endelsebeginpos = 1 ; /fou ze pos wei 1endendendcommand = 5b01000 ; /zui hou shu chu wei 01000endadj_12or24 : /ru guo dang qian zhuang tai weibeginpos = 2 ; /pos wei 2command = 5b10000 ; /command shu chu wei 10000enddefault :beginpos = 0 ; /fou ze zui hou pos wei 0command = 5b00000 ; /comman wei 00000endendcasecase (pos) /pos de case 0 :begin /pos wei 0 shiflash = 3b000 ; /flash wei 000adjbotton = 3b000 ; /adjbotton wei 000end1 : /pos wei 1beginflash = 3b100 ; /flash wei 100if (adjval = 1b0) /ru guo adjval wei 1beginadjbotton = 3b100 ; /adjbotton wei 100endelsebeginadjbotton = 3b000 ; /fou ze wei 000endend2 : /ru guo pos wei 2beginflash = 3b010 ; /flash wei 010if (adjval = 1b0) /ru guo adjval wei 1beginadjbotton = 3b010 ; /adjbotton wei 010endelsebeginadjbotton = 3b000 ; /fou ze wei 000endend3 :beginflash = 3b001 ; /pos wei 3 shi flash wei 001if (adjval = 1b0) /ru guo adjvalbeginadjbotton = 3b001 ; /adjbotton wei 001endelsebeginadjbotton = 3b000 ; /fou ze wei 000endenddefault :beginflash = 3b000 ; /fou ze zui hou flash wei 000adjbotton = 3b000 ; /adjbotton wei 000endendcaseendendmodulemodule displaycontroller (clock, enchange, change, enring, command, hour, getuphour, sleephour, minute,enalarm, getupminute, sleepminute, second, ringtime, pausetime, numa, numb, numc, pm, ring);input clock;input enchange;input change;input enring;input4:0 command;input4:0 hour;input3:0 getuphour;input3:0 sleephour;input5:0 minute;input5:0 getupminute;input5:0 sleepminute;input5:0 second;input4:0 ringtime;input3:0 pausetime;output5:0 numa;reg5:0 numa;output5:0 numb;reg5:0 numb;output5:0 numc;reg5:0 numc;output pm;reg pm;output ring;reg ring;output enalarm;wire enalarm;reg display24;reg enablealarm;wire5:0 time1;wire5:0 time2;always (posedge clock) begin if (enchange = 1b1) /zong kai shi kong zhi begin if (change = 1b1) /bian hua wei yi begin display24 = display24 ; / end end if (enring = 1b0 & command = 5b00000) /command mo shi ling sheng shi neng yu fou begin enablealarm = 12) begin numa 12 pm wei yi pm= 1b1 ; end else begin numa = hour ; /fou ze pm wei 0 pm= 1b0 ; end end else begin numa = hour ; /display wei1 shi pm= 1b0 ; /pm bu liang hour wei numa end numb =minute ; /fen wei numb numc = second ; /miao wei numc end5b00010 : /command wei 00010 shibeginpm= 1b0 ; /pm wei 0numa = getuphour ; /xian shi de shi wei getuphournumb = getupminute ; /xian shi de fen wei numbnumc = 0 ;end5b00100 : /command wei 00100 shi xian shi tiao zheng wan shui shi jianbeginif (display24 = 1b0) /dang display 12 dian shibeginnuma = sleephour - 12 ; /xian shi ye yao bian cheng 12,qie shi pm= 1b1 ;endelsebeginnuma = sleephour ; /dang xian shi 24 xiao shi shi pm 0pm= 1b0 ;endnumb = sleepminute ;numc = 0 ;end5b01000 : /command wei 01000 shi beginpm= 1b0 ; /24 xiao shi xian shinuma = ringtime ; /numa xian shi xiang ling shi jian chang dunumb = 60 ; /numb fu zhi 60numc = pausetime ; /numb xian shi xiang ling zan ting shi jianend5b10000 : /command wei 10000 shibeginpm= 1b0 ; /24 xiao shi xian shi numa = 60 ; /numa 60 fu zhiif (display24 = 1b0) /dang shi 12 xiao shi mo shibeginnumb = 12 ; /numb xian shi 12endelsebeginnumb = 24 ;/ fou ze xin shi 24endnumc = 60 ; /numc wei 60enddefault :beginendendcaseendalways (negedge clock) /xin de bing xing mo kuaibeginif (hour = getuphour) & (minute = getupminute) | (hour = sleephour) & (minute = sleepminute)begin /dang qi chuang huo zhe wan shui ling sheng shi jian shiif (second ringtime) /qie dang miao xiao yu xiang ling chang du shibeginring = 1b1 ; /ling sheng xiang qiendelse if (second time1) /huo dang miao xiao yu time1 shi xiang ling guan diaobeginring = 1b0 ;endelse if (second time2) /huo dang miao xiao yu time2 shi xiang ling kai qibeginring = 1b1 ;endelsebeginring = 1b0 ; /qi ta suo you shi hou xiang ling guan biendendelse if (hour = 7 & minute = 30) | (hour = 8 & minute = 20) | (hour = 8 & minute = 30) | (hour = 9 & minute = 20) | (hour = 9 & minute = 40) | (hour = 10 & minute = 30) | (hour = 10 & minute = 40) | (hour = 11& minute = 30)beginif (second 5) /huo dang te dian shi jian shi xiang ling 5 wei nei you xiaobeginring = 1b1 ;endelsebeginring = 1b0 ;endendelse if (enablealarm = 1b1 & minute = 0 & second 5)begin /enablealarm wei 1 fen wei 0 miao xiao yu 5 xiangring = 1b1 ;endelsebeginring = 50) ? 5 : (numin = 40) ? 4 : (numin = 30) ? 3 : (numin = 20) ? 2 : (numin = 10) ? 1 : 0 ;assign numb = (numin = 60) ? 10 : numin - shi * 10 ;assign numa = shi ;endmodulelibrary ieee; use ieee.std_logic_1164.all; entity num_7seg is port( c:in std_logic_vector(3 downto 0); hex:out std_logic_vector(6 downto 0); end num_7seg; architecture behave_num_7seg of num_7seg is begin with c(3 downto 0) select - hex= 1000000 when 0000 , -0 1111001 when 0001 , -1 0100100 when 0010 , -2 0110000 when 0011 , -3 0011001 when 0100 , -4 0010010 when 0101 , -5 0000010 when 0110 , -6 1111000 when 0111 , -7 0000000 when 1000 , -8 0010000 when 1001 ,-9 -0000000 when 1010 , 1111111 when others; - end behave_num_7seg;module setringlength (clock, en, adjusth, adjusts, ringtime, pausetime);input clock;input en;input adjusth;input adjusts;output4:0 ringtime;reg4:0 ringtime;output3:0 pausetime;reg3:0 pausetime;always (posedge clock)begin : xhdl_1reg0:0 firsttime;if (firsttime = 0)beginringtime = 5 ;pausetime = 2 ;firsttime = 1;endelsebeginif (en = 1b1)beginif (adjusth = 1b1)beginif (ringtime = 20)beginringtime = 1 ;endelsebeginringtime = ringtime + 1 ;endendelse if (adjusts = 1b1)beginif (pausetime = 10)beginpausetime = 1 ;endelsebeginpausetime = pausetime + 1 ;endendendendendendmodulemodule setringtime (clock, en1, en2, adjusth, adjustm, getuphour, getupminute, sleephour, sleepminute);input clock;input en1;input en2;input adjusth;input adjustm;output3:0 getuphour;reg3:0 getuphour;output5:0 getupminute;reg5:0 getupminute;output3:0 sleephour;reg3:0 sleephour;output5:0 sleepminute;reg5:0 sleepminute;always (posedge clock)begin : xhdl_1reg0:0 firsttime;if (firsttime = 0)begingetuphour = 6 ;getupminute = 0 ;sleephour = 22 ;sleepminute = 30 ;firsttime = 1;endelsebeginif (en1 = 1b1)beginif (adjusth = 1b1)beginif (getuphour = 11)begingetuphour = 0 ;endelsebegingetuphour = getuphour + 1;endendelse if (adjustm = 1b1)beginif (getupminute = 59)begingetupminute = 0 ;endelsebegingetupminute = getupminute + 1;endendendif (en2 = 1b1)beginif (adjusth = 1b1)beginif (sleephour = 23)beginsleephour = 12 ;endelsebeginsleephour = sleephour + 1 ;endendelse if (adjustm = 1b1)beginif (sleepminute = 59)beginsleepminute = 0 ;endelsebeginsleepminute = sleepminute +1 ;endendendendendendmodulelibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity clk_1_gen isport(clkin :in std_logic; clkout:out std_logic);end clk_1_gen;architecture behave_clk_div8 of clk_1_gen isconstant N: Integer:=24999999;signal Counter:Integer RANGE 0 TO N; signal Clk: Std_Logic;begin process(clkin) begin if rising_edge(clkin) then -每计到4个（03）上升沿，输出信号翻转一次 if Counter=N then Counter=0; Clk=NOT Clk; else Counter= Counter+1; end if; end if; end process; clkout= Clk; end behave_clk_div8; module fenxian5 (in,out0,out1,out2,out3,out4);input 4:0in;output out0;output out1;output out2;output out3;output out4;assign out0=in0;assign out1=in1;assign out2=in2;assign out3=in3;assign out4=in4;endmodulem