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1 Immediately after the CPU executes an instruction that is neither a branch nor a jump instruction, the program counter (a) remains unchanged(b) is incremented to point to the following instruction(c) is incremented by one(d) has a value that cannot be determined without further information 2 The program counter contains (a) the number of times a program has been executed(b) the address of the CPU instruction that is about to be executed(c) the amount of memory a program is currently using(d) the number of CPU instructions a program has executed so far 3 In one computer, the bytes with addresses A, A+1, A+2 and A+3 contain the integer 256, and the variable declared with int * a; has the value A. In a different computer, the bytes with addresses B, B+1, B+2 and B+3 also contain the integer 256, and the variable declared with int * b has the value B. Which of the following are necessarily true? I The contents of A+1 are equal to the contents of B+1. IIThe contents of A+1 are equal to the contents of B+2.III*a = *b(a) I only(b) III only(c) II and III only(d) I and III only 4 A jump instruction (a) changes the program counter only if its operand is equal to zero(b) changes a pointer to point to the next element of an array(c) increases the program counter(d) unconditionally sets the program counter to its operand 5 A branch instruction (a) sets the program counter to one of many possible values(b) unconditionally sets the program counter to its operand(c) sets the program counter to one of two possible values(d) increases the program counter by a fixed amount 6 A CPU register is a word of CPU memory that (a) records the results of periodic CPU diagnostics(b) is automatically loaded when a CPU instruction refers to a word of normal memory(c) houses a critical variable for the duration of the execution of a program(d) is explicitly loaded and unloaded from normal memory by compiler-generated instructions 7 Which of the following is a good reason (are good reasons) to equip the CPU with small amounts of fast memory? I To make the design of the compiler simpler IITo make some CPU instructions smallerIII To make some CPU instructions faster (a) III only(b) I, II, and III(c) II and III only(d) II only 8 Which of the following numerical operations is most likely to lead to loss of precision? (a) Integer addition(b) Floating-point multiplication(c) Floating-point addition(d) Integer multiplication 9 A memory hierarchy (a) limits programs size but allows them to execute more quickly.(b) takes advantage of the speed of SRAM and the capacity of disk.(c) makes programs execute more slowly but allows them to be bigger.(d) is a way of structuring memory allocation decisions. 10 Compared to dynamic RAM (SRAM), disks are Imore expensive per megabyte.IIslower per word access.IIImore persistent.(a) I only.(b) II only.(c) II and III only.(d) I and III only. 11 When the following code fragment is executed on a computer with 32-bit integers and a fully-associative cache with 32-byte cache lines, how many bytes of the array a will be fetched into the cache from main memory?int a100;for (i = 0; i 17; sum += ai, i+);(a) at most 68.(b) exactly 32.(c) exactly 17.(d) at most 96. 12 Compared to static RAM (SRAM), dynamic RAM (DRAM) isImore expensive per megabyte.IIslower per word access.IIImore persistent.(a) I only.(b) II only.(c) I and III only.(d) II and III only. 13 The 200MHz intel-based processor of a computer with no cache is upgraded to a 500 MHz version of the same processor. On the average, programs now run(a) faster on the internet than off it.(b) about 100% faster (about 1/3 of the memory accesses are instruction fetches).(c) at about the same speed.(d) about 150% faster. 14. Which of the following levels of a typical memory hierarchy transfers data in chunks of smallest size? (a) they all transfer one byte at a time.(b) cache main memory.(c) main memory disk.(d) CPU registers cache. 15. Which of the following manages the transfer of data between the CPU registers and the cache?(a) Operating System.(b) Hardware.(c) Registry.(d) Compiler. 16. Current technology trends suggest that the need for memory hierarchies(a) will disappear once DRAM speeds improve.(b) will
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