键盘扫描及计算器VHDL仿真.doc

电子设计自动化EDA简易计算器设计简易计算器设计 EDA实验报告 一、 实验内容实验要求：完成个位数的加减乘运算，输入用矩阵键盘，输出用数码管显示，每输入一次数据要显示在数码管上。矩阵键盘共16个按键，用其中10个做个位数的输入，用3个分别做加减乘运算，用其中1个做等于操作，各位数的运算结果最多两位，用动态扫描数码管显示运算结果。二、 小组成员三、 实现方法系统组成及连接原理如图所示，主要由由七个功能模块组成：分频模块（为键盘扫描模块和防抖模块提供时钟）、键盘扫描驱动模块（依次置零）、键盘按键值编码模块、键盘编码值防抖模块、运算模块，数码管显示驱动模块、动态扫描驱动模块。分频键值编码防抖键盘矩阵行驱动时钟数码管显示运算数码管动态显示1.分频模块由于FPGA实验板的原始时钟频率高达33.8688MHz，所以不能直接接入设计模块中使用，就需要用到分频模块。将33.8688MHz分频到4KHz和10Hz来使用，一个用于行驱动扫描时钟，一个用于防抖模块。所以，采用写一个可变分频元件来调用。元件视图：主要代码如下（完整代码见附录，下同）：architecture RTL of freq_division iscomponent fredivn isgeneric(n:positive); Port ( clkin:in STD_LOGIC; clkout:out STD_LOGIC);end component;beginU1:fredivngeneric map(n=3)port map(clkin=clk,clkout=clkout_kb);end RTL;仿真结果如下图：达到预期的目的2.行驱动模块（依次对行置零）：键盘扫描的原理就是检测行列信号然后判断出具体是按下了哪一个按键。所以，对行依次置零，当置零频率较快时，按下某一个按键后，一定能得到某一列的信号输出为零，如下图：当行信号为1110时，若按下了0键，就会得到1110的列信号，立马就快可以译码出按键值，若按下4键、8键、C键则都不会有输出。主要代码如下：process(clkin)beginif clr=1 thencount=00; elsif rising_edge(clkin) thenif count=11 thencount=00;elsecount=count+1;end if;end if;end process;process(count)beginif count=01 thenkeydrv=1110;elsif count=10 thenkeydrv=1101;elsif count=11 then keydrv=1011; elsif count=00 thenkeydrv=0111;end if;end process;仿真结果如下图：达到预期的目的3.键值编码模块依据行驱动模块，当按下某一个按键后，立马可以根据行列和并位信号得到唯一的键盘编码值，用5位矢量来保存结果，当没有按键按下时，编码值一直保持着11111不变，并在后端的模块中不对其做任何处理。以下列出部分编码表（完整编码表见附录）：十进制数行&列HEX七段码HEX011101110EE11111107E411011110DE011001133511011101DD10110115B主要代码如下：process(clk)beginif clr=0 thenif rising_edge(clk) thenif temp1=11101110 thenkeyvalue1=00000; -0elsif temp1=11101101 thenkeyvalue1=00001; -1elsif temp1=11101011 thenkeyvalue1=00010; -2elsif temp1=11100111 thenkeyvalue1=00011; -3elsif temp1=11011110 thenkeyvalue1=00100; -4elsif temp1=11011101 thenkeyvalue1=00101; -5elsif temp1=11011011 thenkeyvalue1=00110; -6elsif temp1=11010111 thenkeyvalue1=00111; -7elsif temp1=10111110 thenkeyvalue1=01000; -8elsif temp1=10111101 thenkeyvalue1=01001; -9elsif temp1=10111011 thenkeyvalue1=01010; -10elsif temp1=10110111 thenkeyvalue1=01011; -11elsif temp1=01111110 thenkeyvalue1=01100; -12elsif temp1=01111101 thenkeyvalue1=01101; -13elsif temp1=01111011 thenkeyvalue1=01110; -14elsif temp1=01110111 thenkeyvalue1 test1 test2 test3 test4 test5 test6 test7 test8 test9 test10 test11 test12 test13 test14 test15 test16null;end case;if test1=test5 and test2=test6 and test3=test7 and test4=test8 and test5=test9 and test6=test10 and test7=test11 and test8=test12 and test9=test13 and test10=test14 and test11=test15 and test12=test16 and test1 /= UUUUUUUU then仿真波形如下：从图中可以看出最终temp1从临时信号temp得到最终输出，达到防抖：5.运算模块当前段的模块经过防抖处理以后得到稳定的按键信号，比如1+2=3,转化为编码值就是11101101 10111011 01111101 11100111 = ED BB EB 7D E7(具体编码表见附录)主要代码如下：if ysfh=0 then result=first+second; elsif ysfh=1 then result=first-second; elsif ysfh=2 then result=first*second; end if; n=n+1;elsif n=100 then n=000;end if;end if; end process; process (n) begin if n=001then keyvaluein=conv_std_logic_vector(first,8); elsif n=011then keyvaluein=conv_std_logic_vector(second,8); elsif n=100then keyvaluein=conv_std_logic_vector(result,8); end if; end process;仿真波形如下：以1+3=4 和 5x6=30为例：编码：01 + 03 =04 05 X 06 =1E6.数码管显示模块以及动态扫描模块由于次两个模块是密切相关的，所以统一到一起验证。经过运算得到最终的显示结果后，要在七段数码管中显示，就必须有每一个数的七段码，同时，由于前面的运算模块的结果最大可以达到81，也就是需要8位二进制，两位十进制来表示，所以就必须通过显示模块来分离出十位和个位。分离出十位和个位以后，就必须要利用动态扫描使两个数都能显示出来。因为8个七段数码管的abcdefg位是连在一起的，只有利用分时间隔来显示，一次使能一个数码管，显示一位数，当频率较高时，就可以得到两位数的显示效果。数码管显示模块主要代码如下：if num=0 thenten:=0;one:=10;elsif num0thenten:=0;one:=num;elsif num9 thenten:=1;one:=num-10;elsif num19 thenten:=2;one:=num-20;elsif num29 thenten:=3;one:=num-30;elsif num39 thenten:=4;one:=num-40;elsif num49 thenten:=5;one:=num-50;elsif num59 thenten:=6;one:=num-60;elsif num69 thenten:=7;one:=num-70;elsif num79 thenten:=8;one:=num-80;elsif num89 thenten:=9;one:=num-90;end if;t=conv_std_logic_vector(ten,4);o=conv_std_logic_vector(one,4);动态扫描模块主要代码如下：if count=00 thenshowout=show1;en=00000010;elsif count=01 thenshowout=show2;en showout 0110000 3002 = showout 1101101 6D03 = showout 1111001 79由以上波形可以看出：01 + 02 = 03的计算完成了。五、 总结本次EDA设计实践，完成了从VHDL代码编写到硬件实现的整个流程，掌握了一些FPGA的相关概念以及ISE软件和Active-HDL软件的使用方法。最重要的就是组员之间的合作，因为VHDL程序是模块化编写的，所以不同模块是由不同人来完成编译的，要达到各个模块之间能够良好的衔接通信，就必须有一个很好的沟通交流，把大家的思路集中起来，一起讨论、编写、调试程序。【附录一】完整程序：分频：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fredivn is generic(n:integer:=3); Port ( clkin:in STD_LOGIC; clkout:out STD_LOGIC);end fredivn;architecture Behavioral of fredivn issignal clk1:std_logic:=0;signal counter:integer range 0 to n; beginprocess(clkin) begin if rising_edge(clkin)then if counter=(n-1)/2 then clk1=not clk1; counter=0; else counter=counter+1; end if; end if; end process; clkout=clk1; end Behavioral;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity keyscan is Port ( clr:in std_logic; clkin : in STD_LOGIC; keydrv :out STD_LOGIC_VECTOR(3 downto 0);end keyscan;architecture behavioral of keyscan issignal count : std_logic_vector(1 downto 0); beginprocess(clkin)beginif clr=1 then count=00;elsif rising_edge(clkin) thenif count=11 thencount=00; elsecount=count+1;end if;end if;end process;process(count)beginif count=01 thenkeydrv=1110;elsif count=10 thenkeydrv=1101;elsif count=11 thenkeydrv=1011; elsif count=00 thenkeydrvclkin,keydrv=keydrv1,clr=clr); tempclkin,temp=temp,temp1=temp1,clr=clr);process(clk)beginif clr=0 thenif rising_edge(clk) thenif temp1=11101110 thenkeyvalue1=00000;elsif temp1=11101101 thenkeyvalue1=00001;elsif temp1=11101011 thenkeyvalue1=00010;elsif temp1=11100111 thenkeyvalue1=00011;elsif temp1=11011110 then keyvalue1=00100; elsif temp1=11011101 thenkeyvalue1=00101;elsif temp1=11011011 thenkeyvalue1=00110;elsif temp1=11010111 thenkeyvalue1=00111;elsif temp1=10111110 then keyvalue1=01000;elsif temp1=10111101 thenkeyvalue1=01001;elsif temp1=10111011 thenkeyvalue1=01010;elsif temp1=10110111 thenkeyvalue1=01011;elsif temp1=01111110 thenkeyvalue1=01100;elsif temp1=01111101 thenkeyvalue1=01101;elsif temp1=01111011 then keyvalue1=01110;elsif temp1=01110111 thenkeyvalue1=01111;end if;end if;end if;end process;keycode=keyvalue1;end rtl;防抖：library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity fangdou is port(keycode:in std_logic_vector(4 downto 0);keycode1:out std_logic_vector(4 downto 0);start:out std_logic;clk_f,clr:in std_logic);end fangdou;architecture fangdou of fangdou issignal count1:std_logic_vector(2 downto 0);signal key1:std_logic_vector(4 downto 0);signal key2:std_logic_vector(4 downto 0);signal key3:std_logic_vector(4 downto 0);signal key4:std_logic_vector(4 downto 0);signal key5:std_logic_vector(4 downto 0);signal key6:std_logic_vector(4 downto 0);signal key7:std_logic_vector(4 downto 0);signal key8:std_logic_vector(4 downto 0);signal start_1:std_logic;begin process(clk_f)beginif clr=1 thenkey1=00000;key2=00001;key3=00010;key4=00011;key5=00100;key6=00101;key7=00110;key8=00111;count1=000;start_1=1;elseif rising_edge(clk_f) then if count1=111 thencount1=000; else count1key1key2key3key4key5key6key7key8null;end case;if key1=key2 and key2=key3 and key3=key4 and key4=key5 and key5=key6 and key6=key7 and key7=key8 and key1/=UUUUUthenkeycode1=key1;start_1=0 after 5ns;end if;end process;start=start_1;end fangdou;运算：library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity yunsuan isport(start: in std_logic;keycode1:in std_logic_vector(4 downto 0);keyvaluein:out std_logic_vector(7 downto 0);end yunsuan;architecture Behavioral of yunsuan issignal first,second,result,ysfh: integer range 0 to 99;signal n:std_logic_vector(2 downto 0);begin process(start,keycode1)beginif start=1 thenn=000;else if n=000 thenif keycode1=00001then first=1;elsif keycode1=00010then first=2;elsif keycode1=00011then first=3;elsif keycode1=00100then first=4;elsif keycode1=00101then first=5;elsif keycode1=00110then first=6;elsif keycode1=00111then first=7;elsif keycode1=01000then first=8;elsif keycode1=01001then first=9;elsif keycode1=00000 then first=0;end if;n=n+1;elsif n=001 then if keycode1=01010then ysfh=0; elsif keycode1=01011then ysfh=1; elsif keycode1=01100then ysfh=2;end if; n=n+1;elsif n=010 thenif keycode1=00001then second=1;elsif keycode1=00010then second=2;elsif keycode1=00011then second=3;elsif keycode1=00100then second=4;elsif keycode1=00101then second=5;elsif keycode1=00110then second=6;elsif keycode1=00111then second=7;elsif keycode1=01000then second=8;elsif keycode1=01001then second=9;elsif keycode1=00000then second=0;end if;n=n+1;elsif n=011 and keycode1=01101 then if ysfh=0 then result=first+second;elsif ysfh=1 then result=first-second;elsif ysfh=2 then result=first*second; end if; n=n+1;elsif n=100 thenn=000;end if;end if;end process;process (n)beginif n=001then keyvaluein=conv_std_logic_vector(first,8);elsif n=011then keyvaluein=conv_std_logic_vector(second,8); elsif n=100then keyvaluein=conv_std_logic_vector(result,8);end if; end process;end Behavioral;数码管显示：library IEEE;use IEEE.STD_LOGIC_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity shumaguanxianshi isport(keyvaluein:in std_logic_vector(7 downto 0);clk:in std_logic;show1,show2:out std_logic_vector(6 downto 0);end shumaguanxianshi ;architecture shumaguanxianshi of shumaguanxianshi issignal t:std_logic_vector(3 downto 0); signal o:std_logic_vector(3 downto 0);beginprocess(clk)variable num:integer range 0 to 99;variable ten,one: integer range 0 to 15;beginif rising_edge(clk) thennum:=conv_integer(keyvaluein);if num=0 thenten:=0;one:=10;elsif num0then ten:=0;one:=num;elsif num9 then ten:=1;one:=num-10;elsif num19then ten:=2;one:=num-20;elsif num29then ten:=3;one:=num-30;elsif num39then ten:=4;one:=num-40;elsif num49 then ten:=5;one:=num-50;elsif num59then ten:=6;one:=num-60;elsif num69 then ten:=7;one:=num-70;elsif num79then ten:=8;one:=num-80;elsif num89 then ten:=9;one:=num-90;end if;t=conv_std_logic_vector(ten,4); oshow1show1show1show1show1show1show1show1show1show1show1show2show2show2show2show2show2show2show2show2show2show2=0000000;end case;end if;end process;end shumaguanxianshi ;动态显示：library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity shaomiaoxianshi isport(clk,clr:in std_logic;show1:in std_logic_vector(6 downto 0);show2:in std_logic_vector(6 downto 0);show