Guide(中文版)_430单片机__极端详细__应用程序.doc

1. MSP430 20065 2MSP430 3 MSP430 MSP430(TI)199616(Mixed Signal Pocessor)1.1. MSP430 MSP430MSP430 1 MSP4301.83.6VRAM0.1uA250pAMIPS(MIPS)IO50nAMSP430(FLLFLL+)DCOCPU(AM)5(LPM0LPM4MSP430CPU6usWMIPS()MSP430250uAMIPS(Mcs511020mAMIPS) MSP43050nA(l10uA)MSP430102 MSP43016(RISC)(MCS5112)MSP4308MHz8MIPS(8MIPS168)2530MIPSMSP430DSP16()DMA(FFTDTMF) 4 3 MSP430TI(WDT)AA(Timer_A)B(Timer_B)01(USART0I)101214ADC12DAC12C(DMA)1-6(P1-P6)(Basic Timer)(1011)A/D16(Timer ATimerB)PWM(USART)12CI/O6*8I/OIO(25mA)PIP212A/D200Kb/sLCD160F15xF16x12DAC12C12CDMACPUMSP430 4 DCO_CLKCPUCPUMCLKDCOMSP430- 40+85C 5 MSF430OTFFLASHROM3FLASHOTFROMFLASHJTAGFLASHJTAGFLASHJTAG CPU()PCJTAGCIAR WORKBENCH V3.10FLASHJTAG2001TIBOOTSTRAP()BOOTSTRAP32 5 1.2 MSP430 TI1996MSP430200033x32X3lxMSP43033x32x31xLCDROM(c)OTP(P)EPROM(E)EPROMEPROMOTPROMMSP4303XXFLASHTIMSP4302000F11X11x120I/O20007ADCF13xF14x200172002LCDF4lxF43xF44xTI20032004F15xF16xRAMF1611RAM10KB(RTOS)I2CDMADAC12SVSTIMSP430MSP430FE42xMsP430FW42x()MSP430FG42XMSP430TIMsP430F5XX2530MIPSFLASH(128KB)ISP(CANUSB)MSP430() 6 MSP430F169 2.1 n 1.83.6Vn 330uA1MHz2.2V1.1uA(RAM)0.2uA5n 6usn 16RISC125nsn DMAn 12ADn 12DAn 16Timer_An 16Timer Bn An USART0(UARTSPII2C)n USARTI(UARTSPl)n n n Bootstrap Loadern 2.2 n MSP430F16732KB+256B flash1KB RAMn MSP430F16848KB+256B flash2KB RAMn MSP430F16960KB+256B flash2KB RAMn MSP430F161032KB+256B flash5KB RAMn MSP430F161148KB+256Bflash10KBRAMn MSP430F161255KB+256B flash5KB RAM 7 2.3 MSP430F167MSP430F168MSP430F169 8 MSP430F1610MSP430F1611MSP430F1612 9 2.4 MSP430F15xMSP430F16xMSP430F14xDMA12CDACMSP430F15xMSP430F16xMSP430F15xUSARTMSP430F16xUSART2.5 I/O AVcc 64 ADCDACAVss 62 ADCDACDVcc 1 DVss 63 P1.0/TACLK 12 I/O I/OATACLKP1.1/TA0 13 I/OI/OACCIOAOUTBSLP1.2/TAl 14 I/OI/O/ACCI1AOUTlP1.3/TA2 15 I/OI/OACCl2A0UT2P1.4/SMCLK 16 I/O I/OSMCLKP1.5/TA0 17 I/O I/OAOUT0P1.6/TAl 18 I/O I/OAOUT1P1.7/TA2 19 I/O I/OAOUT2P2.0/ACLK 20 I/O I/OACLKP2.1/TAINCLK 2l I/O I/OAINCLK 10 P2.2/CAOUT/TA0 22 I/OI/OACCIOBP2.3/CA0/TAl 23 I/OI/OAOUTlAP2.4/CA1/TA2 24 I/OI/OAOUT2AP2.5/Rosc 25 I/O I/0DCOP2.6/ADCl2CLK/DMAE0 26 I/OI/OADC12DMA0P2.7/TA0 27 I/O I/OAOUT0P3.0/STE0 28 I/OI/OUSART0/SPIP3.I/SIMO0/DSDA 29 I/OI/OUSART0/SPI/I2CP3.2/SOMIO 30 I/O I/OUSART0/SPIP3.3/UCLK0/SCL 31 I/OI/OUSART0/SPII2CP3.4/UTXD0 32 I/O I/OUSART0/SPIP3.5/URXD0 33 I/O I/OUSART0/SPIP3.6 34 I/O I/OUSART1/UARTP3.7 35 I/O I/OUSART1/UARTP4.0/TB0 36 I/OI/OI/PPWMB7CCR0P4.1/TB1 37 I/OI/OI/PPWMB7CCRlP4.2/TB2 38 I/OI/OI/PPWMB7CCR2P4.3/TB3 39 I/OI/OI/PPWMB7CCR3P4.4/TB4 40 I/OI/OI/PPWMB7CCR4P4.5/TB5 41 I/OI/OI/PPWMB7CCR5P4.6/TB6 42 I/OI/OI/PPWMB7CCR6P4.7/TBCLK 43 I/O I/OTBCLK-B7P5.0 44 I/O I/OUSARTl/SPIP5.1 45 I/OI/OUSARTI/SPIP5.2 46 I/O I/OUSARTI/SPIP5.3 47 I/OI/OUSARTl/SPIUSART0/SPIP5.4/MCLK 48 I/O I/OP5.5/SMCLK 49 I/O I/O 11 P5.6/ACLK 50 I/O I/OP5.7/1TBOUTH/SVSOUT 5l I/OI/OB7SVSPWMP6.0/A0 59 I/O I/O12ADCA0P6.1/Al 60 I/O I/O12ADCA1P6.2/A2 61 I/O I/O12ADCA2P6.3/A3 2 I/O I/O12ADCA3P6.4/A4 3 I/O I/O12ADCA4P6.5/A5 4 I/O I/O12ADCA5P6.6/A6/DAC0 5 I/OI/O12ADCA5DAC0P6.7/A7/DACl 6 I/OI/O12ADCA5DAC1SVSnRST/NMI 58 IBootstrap Load(BSL)TCK 57 ITCKBootstrap LoaderTDI/TCLK 55 ITDITDO/TDI 54 I/OTDO/TDITMS 56 I TMSVeREF+ 10 I VREF+ 7 O VREF-/VREF+ 1l O XIN 8 I XT1XOUT 9 I/O XT1XT2IN 53 I XT2XT20UT 52 O XT2 12 BCS Basic Clock SystemMSP430F169ACLKMCLKSMCLKn n n RTCMSP430F169 13 3.1 31 LFXT1CLK(32.768kHz)450kHz8MHz2 XT2CLK450kHz8MHz3 DCOCLKRC 31 ACLKAuxillary ClockACLKLFXT1CLK1248ACLK2 MCLKMain System ClockMCLKLFXT1CLKXT2CLKDCOCLK1248MCLKCPU3 SMCLKSub System ClockSMCLKXT2CLKDCOCLK12 48SMCLK 14 15 3.2 1 LFXT1 (32.768kHz)XINXOUT12pFLFXT1XTS=0OSCOFF=0LFXT1XTS=1XINXOUTLFXT1CLKSMCLKMCLKOSCOFF=1LFXT12 XT2XT2CLKLFXT1XT2CLKMCLKSMCLKXT2OFFXT23 XT21248MCLKDCOMCLKDCODCOxMODxRSELxDCOCLKSMCLKMCLKSCG0PUCDCOCLKMCLKMCLKLFXT1XT2(1)OSCOFF=1(2)OFIFG=0(3)50us(4)OFIFGOFIFG=1(3)(4)OFIFG0 16 3.3 MSP4630F169 DCO DCOCTL1 BCSCTL12 BCSCTL21 DCOCTL DCODCOx DCO8DCOCLKRSELxMODxDACDCOxDCOx+1DCODCOx7MODx2 BCSCTL1 1XT2OFFXT2XT20 XT21 XT2XTSLFXT1/0 LFXT11 LFXT1DIVAxACLK0 1 22 43 8XT5VXT5V=0RSELxDCO30 .7 17 DCODCOxRSELxDCO3 BCSCTL2 2SELMxMCLK0 MCLKDCOCLK1 MCLKDCOCLK2 MCLKXT2CLK3 MCLKLFXT1CLKDIVMxMCLK0 1 22 43 8SELSSMCLK0 SMCLKDCOCLK1 SMCLKXT2CLKDIVSxSMCLK0 1 22 43 8DCORDCO0 1 18 3.4 /* Basic Clock Module*/#define DCOCTL_ (0x0056) /* DCOCTL */DEFC( DCOCTL , DCOCTL_)#define BCSCTL1_ (0x0057) /* BCSCTL1 */DEFC( BCSCTL1 , BCSCTL1_)#define BCSCTL2_ (0x0058) /* BCSCTL2 */DEFC( BCSCTL2 , BCSCTL2_)/* DCOCTL */#define MOD0 (0x01) /* Modulation Bit 0 */#define MOD1 (0x02) /* Modulation Bit 1 */#define MOD2 (0x04) /* Modulation Bit 2 */#define MOD3 (0x08) /* Modulation Bit 3 */#define MOD4 (0x10) /* Modulation Bit 4 */#define DCO0 (0x20) /* DCO Select Bit 0 */#define DCO1 (0x40) /* DCO Select Bit 1 */#define DCO2 (0x80) /* DCO Select Bit 2 */* BCSCTL1 */#define RSEL0 (0x01) /* Resistor Select Bit 0 */#define RSEL1 (0x02) /* Resistor Select Bit 1 */#define RSEL2 (0x04) /* Resistor Select Bit 2 */#define XT5V (0x08) /* XT5V should always be reset */#define DIVA0 (0x10) /* ACLK Divider 0 */#