笔记本上电时序详解 工厂资料ppt.ppt

30 Sep 2003CharlesYMChenNBProductEngineering SNotePowerSequencePresentation SNoteBlockDiagram SNotePoweronSequence MAX1977 MAX1845 MAX1907 MAX1992 Fuse7A FETPch FETPch FETNch FETNch DC INConnector DockingConnector VINT16 Tsurumai VCC3SW VCCCPUCORE FETNch FETNch LP3958 Fuse0 75A FETPch VCC FAN VCC5B VCC5M USB PWR1 USB PWR2 MICVCC VCC2R5A FETNch VCC3B VCC3M FETPch VCC3AUX VCC3P Fuse2A FETNch VBL16 Fuse2A VCCCPUIO VCC1R5M FETNch FETNch FETNch VCC1R5B VCC1R5AUX FETNch VCCGBEIOAUX VCC1R8M Kenai2 32 ForEthernetController PolySW1 5A VDD15 H8 VCC1R25B LP2996 MAX4245 VCCGMCHCORE MAX1845 VREF MAX1683 FETNch PolySW1 5A MAX8880 VCCACPU MAX1935 VCC1R8M MAX1935 VCC3M VCCGBECOREAUX ICH4M PMH4 CPU PWRSWITCH PWRSW H8 PWRSW H8 PowerButton PWRSW ICH SLP S3 ICH SLP S4 ICH SLP S4 ICH SLP S3 PM SLP S3 PM SLP S5 VTT PWRG VTT PWRG VR PWRGD VR PWRGD PCIRST PWRBTN SLP S3 SLP S4 PWRON B ON VCPU CORE ON DDR VREF MPWRG APWRG BPWRG PCIRST CC CPUPWRGD CC CPUPWRGD PWRGOOD GTL CPURST GTL CPURST GTL ADS MONTARAGM CPURST BPWRG PWROK IMVPOK DOCK PWR16 F 1 2 VREGIN16 2 3 4 4 4 1 4 4 5 5 6 6 6 6 7 7 7 7 7 8 8 8 9 5 5 10 10 10 10 11 11 11 11 11 12 12 13 14 15 16 17 18 19 MPWRG BPWRG PWROK RSMRST Poweronseuqencetable Poweronseuqencetable DOCK PWR16 F VREGIN16 VCC3SW VCC3M ON VCC5M ON Spec VCC3M ON M ON1 toVCC5M ON M ON2 is10ms 20ms VCC3M VCC5M VCC3M VCC MpowerbyMAXIM1977 VCC3M VCC5M VCC1R5M VCC1R8M VCC1R5MpowerbyMAXIM1845 VCC1R8MpowerbyMAXIM1935 VCC1R5M VCC1R8M MPWRG IntheblockofM PGS thevoltageofVCC5MandVCC3Maremonitoredbytheinternalanalogcomparatorrespectively eachstateissuppliedtoM PGSoutput TheterminalisOpendrainstructure Theoperationofdetectionisstartedwhenboth5M ONand3M ONareequaltoHigh TheanalogComparatorhashysteresisvoltageandgeneratehighsignalwhenthefollowingconditionaresatisfied Greaterthan4 461V Typ atpoweronstageof VCC5M RisingEdge andlowerthan4 311V Typ attheshutdownstage Fallingedge after47 5ms 2 5msGreaterthan2 943V Typ atpoweronstageof VCC3M RisingEdge andlowerthan2 793V Typ attheshutdownstage Fallingedge after47 5ms 2 5ms L outputis VCC5M 4 311V Typ VCC3M 2 793V Typ MPWRG Spec VCC3 5MPowertoMPWRGis47 5 5ms ICH SLP S3 ICH SLP S4 Spec DependonICH4Mspec theSLP S4 andSLP S3 shouldriseupafterPoweron SLP S3 toSLP S4 is1RTCCLK 2RTCCLK 1RTCclockisapproximately32us VCC3AUX VCCGBECOREAUX VCC3AUXpowerbyFDC658P VCCGBECOREAUXpowerbyMAXIM1935 VCC3AUX VCCGBECOREAUX VCCGBEIOAUX VCCGBEIOAUX DRV VCC1R5AUX VCC1R5AUX DRV PressPowerButton PressPowerButton PressPowerButton PWRON B ON VCPU CORE ON Spec From PWRONtoB ONis10ms 20ms VCC2R5ApowerbyMAXIM1845 VCC2R5A DDR VREF VCC3B VCC5B VCCACPU VCCGMCHCORE MICVCC VCCCPUIO CorepowerofMotara GMPluspowerbyMAXIM4245 MICVCCpowerbyLP4085 VCCGMCHCORE MICVCC VCCCPUIO CPUI OpowerbyMAXIM1992 VCCGMCHCORE MICVCC VCCCPUIO VCC1R5B VCC1R5B DRV APWRG BPWRG IntheblockofA PGS thevoltageofVCC3Aismonitoredbytheinternalanalogcomparator eachstateissuppliedtoA PGSoutput TheterminalisOpendrainstructure Theoperationofdetectionisstartedwhen3A ONisequaltoHigh TheanalogComparatorhashysteresisvoltageandgeneratehighsignalwhenthefollowingconditionaresatisfied Greaterthan2 943V Typ atpoweronstageof VCC3A RisingEdge andlowerthan2 793V Typ attheshutdownstage Fallingedge InthisperiodA PGSissupplyingHlevel TheHysteresisVoltageareset150mV 50mV AttheHighstate thedelaytimeof350ms 10msisset APWRG BPWRG APWRG BPWRG IntheblockofB PGS thevoltageofVCC5BandVCC3Baremonitoredbytheinternalanalogcomparator eachvoltagestateissuppliedtoB PGSoutput TheterminalisOpendrainstructure Theoperationofdetectionisstartedwhenboth5B ONand3B ONareequaltoHigh TheanalogComparatorhashysteresisvoltageandgeneratehighsignalwhenthefollowingconditionaresatisfied Greaterthan4 461V Typ atpoweronstageof VCC5M RisingEdge andlowerthan4 311V Typ attheshutdownstage Fallingedge after47 5ms 2 5msGreaterthan2 943V Typ atpoweronstageof VCC3M RisingEdge andlowerthan2 793V Typ attheshutdownstage Fallingedge after47 5ms 2 5msInthisperiodB PGSissupplyingHlevel TheHysteresisVoltageareset150mV 50mV AndattheHighstate thedelaytimeisset whenB PGSbecomeHigh thedelaytimeof100ms 5msissetincaseofA PGSisequaltoLow andthedelaytimeof445ms 5msissetincaseofA PGSisequaltoHigh APWRG BPWRG BPWRG 2020 3 16 35 可编辑 APWRG BPWRG Spec FromAPWRGtoBPWRGis100 5ms VTT PWRG VCCCPUCORE VR PWRGD VCCCPUCORE VR PWRGDbyMAXIM1907 VCCCPUCORE VR PWRGD PCIRST CC CPUPWRGD Spec FromBPWRGtoPCIRST is1ms GTL CPURST Spec FromPCIRST toGTL CPURST is1ms GTL ADS LPC FRAME P TRDY P IRDY P FRAME S0TOS3 S0TOS3 S3TOS0 S3TOS0 S0TOS3 S3TOS0POWERSTATUS VCC1R25B S3TOS0 S0TOS3 VCC3B S0TOS3 S3TOS0 S0TOS3 S3TOS0POWERSTATUS VCC5B S0TOS3 S3TOS0 S0TOS3 S3TOS0POWERSTATUS S0TOS3 S3TOS0 S0TOS3 S3TOS0POWERSTATUS VCCACPU S0TOS3 S3TOS0 S0TOS3 S3TOS0POWERSTATUS VCCCPUIO S0TOS3 S3TOS0 S0TOS3 S3TOS0POWERSTATUS VCCGMCHCORE S0TOS3 S3TOS0 S0TOS3 S3TOS0POWERSTATUS VCPUCOREON PWMPOWERON OFFSTATUS MAXIM1977 PLUGINADT SHUTDOWNTHESYSTEM VCC3M PWMPOWERON OFFSTATUS MAXIM1977 PLUGINADT SHUTDOWNTHESYSTEM VCC5M PWMPOWERON OFFSTATUS MAXIM1845 PLUGINADT SHUTDOWNTHESYSTEM VCC1R5M PWMPOWERON OFFSTATUS MAXIM1845 PRESSPOWERBUTTONON SHUTDOWNTHESYSTEM VCC2R5A PWMPOWERON OFFSTATUS MAXIM1907 PRESSPOWERBUTTONON SHUTDOWNTHESYSTEM VCCCPUCORE PWMPOWERON OFFSTATUS MAXIM1992 PRESSPOWERBUTTONON SHUTDOWNTHESYSTEM VCCCPUIO LDOPOWERON OFFSTATUS LP2996 PRESSPOWERBUTTONON SHUTDOWNTHESYSTEM DDR VREF VCC1R25B LDOPOWERON OFFSTATUS MAXIM1935 PLUGINADT SHUTDOWNTHESYSTEM VCC1R8M MAXIM1935 PRESSPOWERBUTTONON SHUTDOWNTHESYSTEM VCCGBECOREAUX LDOPOWERON OFFSTATUS LDOPOWE