基带板原理图设计文档.doc

基带板原理图设计文档1、 系统框图根据与41所沟通，系统框图如下，基带板与RF、主控板、时序板、中频RX和中频TX板的连接关系如下，为了实现LTE基带处理的各种功能和与其他各个处理板的数据交换和接口需要，进行了基带板原理图设计。2、 功能要求：基带板要完成的功能包括：协议软件的处理、物理层软件的处理、系统定时和对RF的控制数据处理。为了完成这些内容，系统包含arm、dsp和fpga三个主要器件，其中ARM完成协议软件处理、DSP负责处理物理层软件中的部分内容、FPGA完成系统定时和物理层算法的部分内容。3、 系统框图ARM:完成操作系统及协议、应用等功能，其支持的借口比较丰富；接口描述：DRAM controller：DDR RAM；SROM controller：FLASH，与DSP、FPGA共用，用于boot代码的存储；FPGA上的RAM，预留，防止协议中有算法需要用硬件实现；双端口RAM1，用于与DSP交换数据；双端口RAM2，用于与41所应用板交换数据；I2C：用于power、clk芯片的控制；I2S：用于codic和blue tooth；SPI：与FPGA间发送控制信息；UART：用于trace;USB：用于应用；GPIO：用于与FPGA和DSP之间产生硬件中断；JTAG：调试接口；DSP:完成物理层流程及算法；EMIFA：FLASH，与ARM、FPGA共用，用于boot代码的存储；FPGA上的RAM，用于与FPGA数据交换；双端口RAM1，用于与ARM交换数据；DDR2：DDR RAM；I2C：与FPGA相连，用于交换控制信息；McBSP0：用于CODICMcBSP1：与FPGA相连，用于交换数据信息；Rapid IO：与FPGA相连，用于交换数据信息；GPIO：用于与FPGA和ARM之间产生硬件中断；FPGA:完成系统定时、射频数据的接收及部分物理层算法；PCI：用于与射频交换数据，需要确认。4、时钟设计LET要求的采样时钟：122.88MHzARM工作时钟：12MHz，可以通过外部的晶振提供或外部的时钟提供；27MHz，用于其中的某些模块，可以选择是否使能；32.768KHz，看门狗时钟；DSP工作时钟：CLKIN1：33.366.6MHz 选50MHzCLKIN2：12.526.7MHz 选25MHzEMIFCLK：160或200 MHz 选 200 MHzSRIO CLK：125或156.25或312.5 MHz 选择 125MHz备156.25MHz系统时钟为20MHz，通过TI的CDCE937产生DSP和ARM的输入时钟OUTFreqY120MHzTo FPGAY225MHzDSPPLL1Y3125MHzSRIOY450MHzDSPPLL2Y5200MHzDSP_EMIFAY612MHzARMY748MHzY8122.88 MHzLTE toFPGAY9122.88 MHz考虑到板子单独使用和与41所接口使用的情况：单独使用安上述设置使用与41所接口使用时，系统时钟由41所射频板提供，时钟为122.88MHz，经过CPLD分频后得到15.36MHz的时钟，再输出到CDCE946后产生相应的其他时钟，输入为：OUTFreqY225MHzDSPPLL1Y3125MHzSRIOY450MHzDSPPLL2Y5200MHzDSP_EMIFAY612MHzARMY748MHzSRIO CLK：125或156.25或312.5 MHz 选择 125MHz 备156.25MHz5电源设计需求：6410电源种类：1.2、1.8V、2.5V、3.3VSignal I/O Description Voltage 推荐值选择值VDDALIVE P Internal power for alive block 1.2 1.2VDDARM P Internal power for ARM1176 core and cache 1.1/1.2 1.2VDDINT P Internal power for logic 1.2 1.2VDDMPLL P Power for MPLL core 1.2 1.2VDDAPLL P Power for APLL core 1.2 1.2VDDEPLL P Power for EPLL core 1.2 1.2VDDOTG P Power for USB OTG PHY 3.3 3.3VDDOTGI P Internal power for USB OTG PHY 1.2 1.2VDDMMC P IO power for SDMMC 1.83.3 3.3VDDHI P IO power for Host I/F 1.83.3 3.3VDDLCD P IO power for LCD 1.83.3 3.3VDDPCM P IO power for PCM (Audio I/F I2S, AC97) 1.83.3 3.3VDDEXT P IO power for external I/F (UART, I2C, Camera I/F, etc.) 1.83.3 3.3VDDSYS P IO power for system control. (Clock, reset, operation mode, JTAG, etc) 1.83.3 3.3VDDUH P Power for USB Host 3.3 3.3VDDADC P Power for ADC core and IO 3.3 3.3VDDDAC P Power for DAC core and IO 3.3 3.3VDDRTC P Power for RTC logic and IO 1.83.0 2.5VDDM0 P IO power for Memory Port 0 1.83.3 3.3VDDSS P IO power for ATA IO muxed in MEM0 port 1.83.3 3.3VDDM1 P IO power for Memory Port 1 1.8/2.5 1.86455电源种类：1.2v、1.8v、3.3vSignal I/O Description Voltage 推荐值选择值VREFSSTLA(DVDD18/2)-V reference for SSTL buffer (DDR2 Memory Controller). This inputvoltage can be generated directly from DVDD18 using two 1-kW resistors to forma resistor divider circuit.1.8V/2VREFHSTLA(DVDD15/2)-V reference for HSTL buffer (EMAC RGMII). VREFHSTL can begenerated directly from DVDD15 using two 1-kW resistors to form a resistordivider circuit.1.5V/2DVDDRS1.8-V I/O supply voltage.（SRIO regulator supply）1.8V1.8AVDDAASRIO analog supply:1.25-V I/O supply voltage (-1000 and -1200 devices)1.2-V I/O supply voltage (-850 and -720 devices).Do not use core supply.1.25V1.2V1.2AVDLL1A1.8-V I/O supply voltage.1.8V1.8AVDLL2A1.8-V I/O supply voltage.1.8V1.8DVDDRMSSRIO interface supply:1.25-V core supply voltage(-1000 and -1200 devices)1.2-V core supply voltage (-850 and -720 devices).the source for this supply voltage must be the same as that of CVDD1.25V1.2V1.2DVDD12SMain SRIO supply:1.25-V I/O supply voltage (-1000 and -1200 devices)1.2-V I/O supply voltage (-850 and -720 devices).Do not use core supply.1.25V1.2V1.2AVDDTASRIO termination supply:1.25-V I/O supply voltage (-1000 and -1200 devices).1.2-V I/O supply voltage (-850 and -720 devices).Do not use core supply.1.25V1.2V1.2DVDD15S1.8-V or 1.5-V I/O supply voltage for the RGMII function of the EMAC.1.8V1.5V1.8DVDD18S1.8-V I/O supply voltage (DDR2 Memory Controller)1.8V1.8DVDD33S3.3-V I/O supply voltage3.3V3.3CVDDS1.25-V core supply voltage (-1000 and -1200 devices).1.2-V core supply voltage (-850 and -720 devices).1.25V1.2V1.2FPGASignal I/O Description Voltage VCCAUX2.5VCCINT1.0VCCO电源选择：FPGA：VCCAUX2.53ATPS74401VCCINT1.010APTH04T240WVCCO3.310APTH04T240W1.86APTH08T230W/TPS51100DSP、ARM1.2TPS650511.8PTH08T230W3.3PTH04T240W1.25PTH04T240W6、FPGA模式选择：Configuration Mode M2:0 Bus Width CCLK Direction Master Serial 000 1 Output Master SPI001 1 Output Master BPI-Up010 8, 16 Output Master BPI-Down011 8, 16 Output Master SelectMAP100 8, 16 Output JTAG 101 1 Input (TCK) Slave SelectMAP 110 8, 16, 32 Input Slave Serial 111 1 Input 我们系统中选择JTAG或Slave SelectMAP，所以M2固定为高，M1:0为01则为JTAG，为10即为Slave SelectMAP，为11则为slave serialSlave SelectMAP模式下：可以设置为DSP boot 还是arm boot，需要的信号：CCLK： 写使能CS_B： 片选RDWR_B：GPIOslave serial模式下：可以设置为DSP boot 还是arm boot，CCLK： GPIOD_IN： GPIO7、DSP设置：AEA19/BOOTMODE3AEA18/BOOTMODE2AEA17/BOOTMODE1AEA16/BOOTMODE0设置Boot模式：0000 - No boot (default mode)0001 - Host boot (HPI)0010 -Reserved0011 - Reserved0100 - EMIFA 8-bit ROM boot0101 - Master I2C boot0110 - Slave I2C boot0111 - Host boot (PCI)1000 thru 1111 - Serial Rapid I/O boot configurationsCFGGP2:0 pins must be set to 000b during reset for proper operation of the PCI boot mode.AEA15/AECLKIN_SEL0 EMIFA 输入时钟选择0 - AECLKIN (default mode)1 - SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software selectable via the Software PLL1 Controller. By default, SYSCLK4 isselected as CPU/8 clock rate.AEA14/HPI_WIDTH1HPI总线宽度选择0 - HPI operates as an HPI16 (default). (HPI bus is 16 bits wide. HD15:0pins are used and the remaining HD31:16 pins are reserved pins in theHi-Z state.)1 - HPI operates as an HPI32.AEA13/LENDIAN设置 Device Endian mode (LENDIAN)0 - System operates in Big Endian mode1 - System operates in Little Endian mode(default)AEA12/UTOPIA_EN1UTOPIA Enable bit (UTOPIA_EN)UTOPIA peripheral enable(functional)0 - UTOPIA disabled; Ethernet MAC (EMAC) and MDIO enable(default).EMAC/MDIO configuration (interface)MII, RMII, GMII or the standalone RGMII is controlled by theMACSEL1:0 bits.1 - UTOPIA enabled; EMAC and MDIO disabled except when the MACSEL1:0 bits = 11 then, the EMAC/MDIO RGMII interface is still functional.And if MACSEL1:0 = 11, the RGMII standalone pin functions can be used.AEA111必须接1k下拉电阻AEA10/MACSEL1AEA9/MACSEL0EMAC/MDIO interface select bitsAEA8/PCI_EEAI0AEA8: PCI auto-initialization via external I2C EEPROMIf the PCI peripheral is disabled (PCI_EN pin = 0), this pin must not bepulled up.0 - PCI auto-initialization through I2C EEPROM is disabled (default).1 - PCI auto-initialization through I2C EEPROM is enabled.AEA7AEA6/PCI660PCI Frequency Selection (PCI66)0 - PCI operates at 33 MHz (default).1 - PCI operates at 66 MHz.If the PCI peripheral is disabled (PCI_EN = 0), this pin must not bepulled up.AEA5/MCBSP1_EN0McBSP1 Enable bit (MCBSP1_EN)0 - GPIO pin functions enabled (default).1 - McBSP1 pin functions enabled.ASEYAS4C/LKOUT_EN0SYSCLKOUT Enable pin (SYSCLKOUT_EN)0 - GP1 pin function of the SYSCLK4/GP1 pin enabled (default).1 - SYSCLK4 pin function of the SYSCLK4/GP1 pin enabled.AEA31SRIO使能： 上拉SRIO不使能：下拉AEA2