FPGA程序加法器.doc

顶层设计程序library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity JIA is PORT(clockin: in std_logic; resetin:in std_logic; kbin : in std_logic_vector(3 downto 0); kbout : out std_logic_vector(2 downto 0); segment_out : out STD_LOGIC_VECTOR(6 downto 0); sweepout : out STD_LOGIC_VECTOR(3 downto 0); end JIA;architecture Behavioral of JIA is COMPONENT keyboard isport(clk,reset : in std_logic; kb_in : in std_logic_vector(3 downto 0); c,d: out std_logic_vector(3 downto 0); seg1,seg2 : out std_logic_vector(6 downto 0); swo,so: out std_logic; kb_out : out std_logic_vector(2 downto 0); END COMPONENT; COMPONENT add isport ( a,b: in std_logic_vector(3 downto 0); s1,s2: in std_logic;s: out std_logic_vector(4 downto 0); END COMPONENT;COMPONENT yima isport(Clock,reset : in std_logic; seg3,seg4 : out std_logic_vector(6 downto 0); sin: in std_logic_vector(4 downto 0); END COMPONENT;signal e,k: STD_LOGIC;signal f,g : std_logic_vector(3 downto 0);signal h : std_logic_vector(4 downto 0);signal segment_out1 : STD_LOGIC_VECTOR(6 downto 0);signal segment_out2 : STD_LOGIC_VECTOR(6 downto 0);signal segment_out3 : STD_LOGIC_VECTOR(6 downto 0);signal segment_out4 : STD_LOGIC_VECTOR(6 downto 0); type state_type is (z0,z1,z2,z3);signal state: state_type;signal div:std_logic_vector(26 downto 0):=(others=0);signal clk:std_logic; BEGIN process(clockin) begin if rising_edge(clockin) then div=79999 then div0);end if;if div=39999 thenclk=1;else clkstatestatestatestateclockin,kb_in=kbin,reset=resetin,c=f,d=g,swo=e,so=k,seg1=segment_out1, kb_out=kbout,seg2=segment_out2); u2: add PORT MAP(a=f,b=g,s=h,s1=k,s2=e); u3: yima PORT MAP(Clock=clockin,sin=h,reset=resetin,seg3=segment_out3,seg4=segment_out4); with state seLectsweepout=1110 when z0, 1101 when z1, 1011 when z2, 0111 when z3; with state seLectsegment_out 0);signal clkdiv:std_logic;signal kb_out_s:std_logic_vector(2 downto 0):=010;signal kb_in_s:std_logic_vector(3 downto 0):=0001;signal m,c1,d1 : std_logic_vector(3 downto 0):=0000;beginkb_out = not kb_out_s;kb_in_s = not kb_in ;c = c1 ;d = d1 ;process(clk) begin if rising_edge(clk) then div=div+1;end if;end process;clkdiv= div(14) ;process(clkdiv)begin if (clkdivevent and clkdiv=1) then kb_out_sm =0000;swo =0;so m =0001;swo =0;so m =0010;swo =0;so m =0011;swo =0;so m =0100;swo =0;so m =0101;swo =0;so m =0110;swo =0;so m =0111;swo =0;so m =1000;swo =0;so m =1001;swo =0;so swo =1; c1 so =1; d1 null; end case; end if; end process;process(clk)begin if(reset=0)then seg1 seg1 seg1 seg1 seg1 seg1 seg1 seg1 seg1 seg1 seg1 null; end case; end if; end process; process(clk)begin if(reset=0)then seg2 seg2 seg2 seg2 seg2 seg2 seg2 seg2 seg2 seg2 seg2 null; end case; end if; end process; end Behavioral;加法实现library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity add isport ( a,b: in std_logic_vector(3 downto 0); s1,s2: in std_logic;s: out std_logic_vector(4 downto 0);end entity;architecture Behavioral of add is signal aa,bb,ss:std_logic_vector(4 downto 0);beginaa=0& a;bb=0& b;process(aa,bb,s1,s2)begin if (s1=1 and s2=1) thenss= aa+bb; end if; s=ss;end process;end Behavioral;译码显示library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity yima isport(Clock,reset : in std_logic; seg3,seg4 : out std_logic_vector(6 downto 0); sin: in std_logic_vector(4 downto 0); end yima;architecture Behavioral of yima is beginprocess(Clock,sin) begin if(reset=0)then seg3 =1000000; seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1000000;seg4 seg3 =1111001;seg4 seg