cadence快捷键.doc

原理图：i放大 o缩小 ctrl+mouse 放大缩小 ctrl+pageup ctrl+pagedown 左右移动 ctrl+n 下一PART ctrl+b 上一PART view-package 查看全部Part view-part 查看某一PART edit-browse 查看part、nets等 alt断开连接移动 R旋转， V垂直， H水平原理图 R 旋转 shift 任意角度走线 alt拖动元件时切断连接全局修改器件属性：edit-browse-parts-shift全选所有器件-edit-properties-browse spreadsheet修改即可。原理图库：D:CadenceSPB_16.3toolscapturelibraryDiscrete.olb (散件)建立原理图库：new-libraryCadence olb ：ctrl+N 切换到下一PART ctrl+B 切换到前一PART栅格的控制都在options-preferences-Grid DisplaySchemtic page grid控制原理图栅格Part and symbol grid控制元器件库栅格*PCB例程：D:CadenceSPB_16.3sharepcbexamplesboard_design测量距离：display-measure / Find-pinsPCB Editor：右键-cancel 取消 类、子类 color visiblePCB提供两种模式，布局布线，封装库（package symbol）PCB 封转库中，怎样设置图纸大小？ 显示栅格大小？焊盘元件封装 layout-pins:x0 0 -右键donedra place_bound_top(矩形) silkscreen_top = assemble_top assemble_top:x0 0.75 ix 1.8 iy -1.5 ix -1.8 iy 1.5 (add line) silkscreen_top: x0.6 0.94 ix -1.38 iy -1.88 ix 1.38 (add line) x1.2 0.94 ix 1.38 iy -1.88 ix -1.38 place_bound_top:add rectangle x-0.85 1 x2.65 -1 参考标号：layout-label-refdes Assembly_top 内部 Silkscreen_top 左上角 file-new-package symbol 必须有：1引脚2零件外形，轮廓线3参考编号4place_bound放置安装区 psm元件封装数据文件，dra元件封装绘图文件BGA272封装：球形引脚0.75 宽27mm IPC标准 PCB上 80% 0.6 pad designer pad-package symbol file-new smd0_60cir solder大0.1 checkpcb editor:package symbol dsp6713bga272 setup-drawing parameters 设置尺寸 -5 -36 41 41 setup-grids 0.0254 layout-pins x0 0 x0 -1.27 右键-done edit-delete find-all off-pinspackage geometry: place_bound_top:add rectangle x-3.45 3.45 x27.55 -27.55 silkscreen_top:0.2 x-1.45 1.45 x 25.55 1.45(x间有空格） x 25.55 -25.55 x -1.45 -25.55 x -1.45 1.45 silkscreen_top:加角标 addline 0.2 加点 assembly_top:add line 参考标号：assembly_top 内部 silkscreen_top 左上角SOIC焊盘：不规则 建立图形-pad-package pcb editor:shape symbols cir+rect+cir setup-drewing param: -2 -2 4 4 setup-grid:0.0254 shape-rectangle:etch x -0.625 0.3 x 0.625 -0.3 shape-circle x -0.625 0 x -0.925 0 x 0.625 0 x 0.925 0 shape-merge shapes(融合) create symbol rx1_85y0_6r0_3.ssm(图形零件文件） 又一个rx2_05y0_8r0_4.ssm soldermaskpad designer: 设置工作路径：setup-user preference 设置旋转+右键旋转 设置引脚旋转 package symbols通孔焊盘 大10mil pcb editor flash symbol .fsm add flash 1.5 1.8 开口spoke width 0.7 anti padbrd pcb editor 设置尺寸 setup-drawing 精度 mil 2 -4000 -4000 18000 12000 板框 add line board geometry outline x 0 0 ix5400 iy 4000 ix -5400 iy -4000倒角 manufacturer -dimension fillot(圆弧角） 80mil 点角的两线 route keep in ：setup-areas-route keepin route keepin -all - unfilled x 100 100 ix 5200 iy 3800 ix -5200 iy -3800 package keep in: edit-z-copy 图形复制（shape） package keepin -all 点击route keepin find-shape 安装孔：place-manually-placement -advance seting-library placement list-package symbols-mtg300_600 edit-move find-symbols x 220 220 x 220 3780 x 5180 220 x5180 3780设置层叠结构 setup-cross-section -layout cross section (内电层plane)内电层覆铜 edit-z-copy find-shape option-etch-GND-create dynamic shape power-create dynamic shape导入网表：file-import logic -cadence-import directory place- manually设置栅格点：setup-grids onsetup-drawing options:status/dispaly 需经常查看pcb布局 手工place：place-manually autohide:右键show mirror：option、右键、setup-draw option-symbols -mirror 已放置元件：edit-mirror 旋转:已放置：move -右键rotate option-angle-放置后右键旋转-增量 移动：edit-move (框选多移动)交互式布局：原理图option-preference-enable intertool (millsce) PCB:placement 原理图选中元件-右键PCB editor select(shift+s) 一page布局到PCB：原理图：edit-browers-part-shift全选元件-edit-priority-new-PAGE 1 dsn-tools-create netlist-setup -configuration file-edit PAGE=YES-Allow user defined propity PCB:file-import logic-create user-defined priorities- place-quick place -place by property/value-right-place room布局：可从PCB或SCH中设置room属性 PCB：edit-properties-find by name-comp(or pin)/name-more-选器件-apply- room-value:power3v3-apply-show-ok setup-outline-room outline-create place-quick place-place by room-place-ok SCH: 选器件(ctrl)-右键-property-cadence-allegro-room-右键edit- current properties-apply dsn-tools-create netlist PCB-file-import logic-setup-outline-room outline.一次调进所有元件quick place:place-quickplace-place all components-around package keepin-right 关掉线属性-display-black rats-all edit-move-find by name -U6常用命令：edit-move / mirror干扰源：时钟，RAM(bus，高速) LDO线性电源噪声小， 开关电源噪声大平面去耦 管脚去耦电容值越小越靠近管脚排阻用于端接1.去耦电容2.端接电阻时钟走线 线比较宽*约束规则设置：setup-constraints standard values space-set values physical(line/vias) rule set - default 线变窄-neck 8mil精装线 设置过孔physical rule set设置规则值：1设置约束规则setup-constraints 2设置网络属性名edit-property-find-net-more-apply-net physical type-apply net spacing type 3网络赋值规则 电源20mil特殊区域处理：setup-constraints-areas require a type property-add- attach property-点shape-edit property窗口设置属性名- 网络赋值规则布线：route-connect设置规则：布线 建立总线：constraint Manager-Net-Routing-wiringmcu-rammcu-flash 两者距离相等最好在总线基础上建立拓布后，设置规则 拓扑约束：选择线-logic-net schedule-选择引脚-右键insert T 方法2.总线-右键sigx-在SigXplorer编辑连线-set constraint-wiring-template-verify-file update constraint manager 走线线长规则设置：sigx-set constraint-prop delay-from to length(max min)-add-update constraint manageranalyze -analysis modes 打开拓布、线长显示 等长设置：蛇形走线 调整传播延时 sigx-set constraint-rel prop delay- T性连接点后两段相等：new-T.1 - U7 local-length tolerance:500mil-add (T.1- U7 T.1 - U8) mcu到器件：new-u6-U7 global-length:400mil-add 查看：net-routing-relative propagation 差分对设置： constraint manager-选线-右键create differential pair constraint manager-net-routing- differential Pair-设置 (phase tolerance 10mil 两线容忍误差） 方法2.logic-assign differential pair -选线-添加 setup-constraints-electrical constraints-diffPair value-new-设置 assign-赋值布线前准备47： 设置颜色：display-color-设置stack up、components、 manufacturing、geometry 屏蔽电源地线：edit-property-find name net-more-power -apply-ratsnest_schedule-power_and_ground-apply 高亮显示：display-color -display -highlight设置颜色-display-highlight setup-user preferences-display -display_nohilitefont drc： display drcfill setup-draw options-display 设置DRC尺寸 飞线显示：display-show rats-all components nets 关闭：blank rats-all components nets 不同网络高亮不同颜色：display-highlight-find net ；option 选择高亮颜色-点击网络BGA fan out48:route -fanout by pick-find components-点选器件(电源地未fanout) constraints-电源线宽属性去掉 右键setup-fanout-direction anywhere布线：route-connect-option设置 设置过孔：setup-constrant-physical-via设置布线方式50： 换层：双击/右键add via 、 swap layer 群组走线51：bus走线 route-connect 1.框选网络 2.右键temp group，逐个点击pin 线距：右键route space 动态显示延迟：setup-etch-allegro_dynam_timing on/ allegro_dynam_timing_fixedpos 确认 rdly相对延迟 dly延迟当前走线长度：setup-etch-allegro_etch_length_on 确认router-slide 修复走线router-miter by pick 修正转角为45router-spread between voids让开过孔边界router-gloss差分对布线：53T型走线：蛇形走线:route -delay tune - trombone较好覆铜55：shape-polygen 多边形 /rectanglar 矩形 /circular 圆形 shape-edit boundary 附网络：shape-select shape or void-点击铜皮-assign net-option 选择网络 手工挖空：shape-manual void-形状 删除孤岛：shape-delete islands 铜皮合并：shape-merge shapes内电层分割：add-line- option-anti etch -power-width 40mil间距 edit-splite create-power 删除孤岛布线完成后：测试点57：PCB编号：logic-auto rename refdes-rename-设置 原理图edit-back Annotate查看：tools-report/quick reports:unconected pins report 数据库检查：tools-update DRC /db checksilkscreen58drill 59artwork60内电层覆铜？*丝印*silkscreen:关闭走线层，打开丝印层。 display-display and visibility-stack up-etch 关闭 asembly top/bottom off manufacturing-autosilk_top/autosilk_bottom on 生成丝印：manufacture-silkscreen-package geometry:silk reference designator:silk -silkscreen 改变字体大小：edit-change-find:text-option:width 8 block 2-框选板子-右键done 调整位置：edit-move 添加文字：add-text-option:manufacturing:autosilk_top*钻孔文件*钻孔文件相关操作：drl 设置参数 manufacture-Nc-NC parameters-设置参数(默认) = nc