FPGA 交通灯控制器实验.doc

交通灯控制器 一、实验目的 熟练掌握EDA软件quartus 2的应用环境,加强利用verilog语言解决生活中实际问题的能力。二、实验原理和内容 利用软件quartus 2进行编写程序实现十字路口交通灯控制器，达到A方向和B方向红、黄、绿三盏灯按合理的顺序亮或灭，并能将灯亮的时间用倒计时的形式显示在数码管上，最后通过软件自带的工具将交通灯控制器的门级电路和RTL级电路自动生成。三、实验步骤1：首先分析交通灯的原理，整理出所需要的模块，设定每个灯的亮灯时间。2：运行 quartus 2软件、新建工程，然后新建verilog HDL文件，利用verilog语言编写程序实现A和B方向的红黄绿三盏灯合理的交替亮灭，通过对应数码管显示亮灯倒计时。3：编译程序，若有错误根据错误提示对程序进行修改，直到编译通过，然后设置LED灯和数码管的引脚，以达到控制A和B那盏灯亮和与之相对应的数码管做倒计时，倒计时结束，亮灯状态转换的效果。4：将程序烧入FPGA开发板，观察开发板上的LED和数码管显示状况，看是否达到实验目的，若达到则记录实验结果并整理，反之继续修改，直到达到预期效果为止。5：关闭电源，拆除实验器材。4、 实验数据A方向红灯40s,黄灯10s,绿灯30sB方向红灯40s,黄灯10s,绿灯30s五、实验代码module traffic(clk,en,seg,dig,lampa,lampb); input clk;/时钟信号，50Mhz input en;/ 使能信号，当为高电平时控制器工作，当为低电平时，进行初始化设置。 output7:0 dig;/数码管位选 output7:0 seg;/数码管段选 output2:0 lampa;/A方向灯亮的情况 output2:0 lampb;/B方向灯亮的情况 reg clk_out1; reg clk_out2; reg15:0 count1; reg31:0 count2; reg1:0 a; reg2:0 lampa; reg2:0 lampb; reg3:0 disp_dat; reg7:0 dig; reg7:0 seg; reg7:0 ared,ayellow,agreen,bred,byellow,bgreen; reg7:0 numa,numb; reg tempa,tempb; reg1:0 counta, countb; always (posedge clk) begincount1=count1+1;if(count1=16d25000)beginclk_out1=clk_out1;count1=0;endend always (posedge clk) begincount2=count2+1;if(count2=32d25000000)beginclk_out2=clk_out2;count2=0;endend always (en) /给各种灯亮的时间预置数，注意此处为十六进制的数begin if (!en) begin ared = 8h40;ayellow = 8h10;agreen = 8h30;bred =8h40;byellow = 8h10; bgreen = 8h30; endend always (posedge clk_out2) /控制A方向的四种灯的亮灭及亮的时间 begin if(en) begin if(!tempa) begin tempa = 1; case(counta) 2d0:begin numa = ared; lampa = 3b011; counta = 2d1;end 2d1:begin numa = agreen; lampa = 3b110; counta = 2d2;end 2d2:begin numa = ayellow; lampa = 3b101; counta = 2d0;end endcase end else begin if(numa3:0=0) begin numa3:0 = 4d9; numa7:4 = numa7:4-1; end else numa3:0 = numa3:0-1; if (numa = 8d2) tempa = 0; end end else begin lampa = 3b000; counta = 0; tempa = 0; end end always (posedge clk_out2) /控制B方向的四种灯的亮灭及亮的时间 begin if(en) begin if(!tempb) begin tempb = 1; case(countb) 2d0:begin numb = bgreen; lampb = 3b110; countb = 2d1;end 2d1:begin numb = byellow; lampb = 3b101; countb = 2d2;end 2d2:begin numb = bred; lampb = 3b011; countb = 2d0;end endcase end else begin if(numb3:0=0) begin numb3:0 = 4d9; numb7:4 = numb7:4-1; end else numb3:0 = numb3:0-1; if (numb = 8d2) tempb = 0; end end else begin lampb = 3b000; countb = 0; tempb = 0; end end always (posedge clk_out1) begin a=a+1;end always (posedge clk_out1) begincase(a) /数码管显示什么样的数2d0:disp_dat = numa3:0;2d1:disp_dat = numa7:4; 2d2:disp_dat = numb3:0; 2d3:disp_dat = numb7:4;endcasecase(a)/数码管位选2d0:dig = 8b10111111;2d1:dig = 8b01111111;2d2:dig = 8b11111110; 2d3:dig = 8b11111101;endcaseend always (disp_dat)begincase(disp_dat)/数码管译码4h0:seg = 8hc0;/显示04h1:seg = 8hf9;/显示14h2:seg = 8ha4;/显示24h3:seg = 8hb0;/显示34h4:seg = 8h99;/显