HBE-EMPOSIII-SV210实验箱的构成.doc

1. 实验目的：了解三星S5PV210处理器的结构及特点；掌握HBE-EMPOSIII-SV210的系统构造及特征。2. 实验内容：对照实验箱，阅读并理解以下资料。阅读材料：3. HBE-EMPOSIII-SV210 系统概要3.1 S5PV210 处理器构造及特征HBE-EMPOSIII-SV210基于采用ARM公司CortexTM-A8内核的三星S5PV210，是一种嵌入式教学用具。在了解HBE-EMPOSIII-SV210的系统结构之前，我们将对S5PV210做简要说明，并简单了解一下处理器的结构及特点。图 11 S5PV210 的框图S5PV210的框图如图1-1所示。从图中可知，S5PV210由ARM内核、系统外围设备（System Peripheral）、多媒体（Multimedia）、存储器接口（Memory Interface）、电源管理（Power Management）、连通性（Connectivity）等功能块构成。S5PV210基于三星开发的ARM CortexTM -A8，是一种实现ARM架构V7-A的32位RISC微处理器。它为要求低耗电、高性能的移动及普通应用提供解决方案。此外，为提供3G和3.5G通信服务相关的优化硬件性能，S5PV210还具有64位内部总线结构。S5PV210针对动作视频处理（Motion Video Processing）、显示控制及缩放（Display Control And Scaling）等，内置了多个功能强大的硬件加速器。其中，MFC（Multi Format Codec，多格式编码译码器）提供了有关MPEG-1/2/4、H.263/H.264的编码和解码，还提供了有关VC1、Divx的解码。此外，这种硬件加速器还支持实时电视会议和模拟电视输出、HDMI接口。.S5PV210 的特征如下。 ARM CortexTM-A8 based CPU Subsystem with NEON 32/32KB I/D Cache, 512KB L2 Cache Operating frequency up to 800 Mhz at 1.1V, 1 GHz at 1.2V 64-bit Multi-layer bus architecture MSYS domain for ARM CortexTM-A8, 3D engine, Multi Format Codec and Interrupt Controller Operating frequency up to 200 Mhz at 1.1V DSYS domain mainly for Display IPs(such as LCD controller, Camera interface, and TVout), and MDMA Operating frequency up to 166 Mhz at 1.1V PSYS domain mainly for other system component such as system peripherals,external memory interface, peri DMAs, connectivity IPs, and Audio interfaces. Operating frequency up to 133 Mhz at 1.1V Audio domain for low power audio play Advanced power management for mobile applications 64KB ROM for secure booting and 128KB RAM for security function 8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p30fps and coding of MPEG-2/VC1/Divx video up to 1080p30fps. JPEG codec support up to 80 Mpixels/s 3D Graphics Acceleration with programmable shader up to 20M triangles/s and 1000 Mpixels/s 2D Graphics Acceleration up to 160MPixels/s 1/2/4/8 bpp Palletized or 8/16/24bpp Non-Palletized Color-TFT recommended up to XGA resolution. TV-out and HDMI interface support for NTSC and PAL mode with image enhancer MIPI-DSI and MIPI-CSI interface One AC-97 audio codec interface and 3-channel PCM serial audio interface 3-channel 24-bit I2S interface 1-channel TX only S/PDIF interface support for digital audio 3-channel I2C interface 2-channel SPI interface 4-channel UART including 3Mbps port for Bluetooth 2.0 On-chip USB 2.0 OTG supporting high speed (480Mbps, on-chip transceiver) On-chip USB 2.0 Host Asynchronous Modem Interface 4 SD/SDIO/HS-MMC interface. ATA/ATAPI-6 standard interface 24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA) 14x8 key matrix interface 10-channel 12-bit multiplexed ADC Configurable GPIOs Real time clock, PLL, timer with PWM and watch dog timer. System timer support for accurate tick time in power down mode(except sleep mode) Memory Subsystem Asynchronous SRAM/ROM/NOR Interface with x8 or x16 data bus. NAND Interface with x8 data bus Muxed/Demuxed OneNAND Interface with x16 data bus. LPDDR1 Interface with x16 or x32 data bus (266400Mbps/pin DDR) DDR2 interface with x16 or x32 data bus (400Mbps/pin DDR) LPDDR2 interface (400Mbps/pin DDR)3.2 HBE-EMPOSIII-SV210的系统构造及特征在本节中，记述了目标板 HBE-EMPOSIII-SV210 的系统构造及特征。3.2.1 系统构造HBE-EMPOSIII-SV210以S5PV210处理器为中心，主要由CPU模块（由NAND Flash memory、DDR2 SDRAM和缓存等构成）、通过NOR Flash Memory、LCD、UART、USB、Audio、Ethernet、Camera、SD Card slot等外围设备和FPGA控制的DipSwitch、DotMatrix、LEDs、CharacterLCD、OLED、7-Segment、蜂鸣器、Keypad、CMOS Camera等多种应用设备以及基板（提供通过Microcontroller控制的各种传感器）构成。下图 1-2 显示了 HBE-EMPOSIII-SV210 的整体框图。图 12 HBE-EMPOSIII-SV210 整体框图3.2.2 系统特征HBE-EMPOSIII-SV210主要由CPU模块和基板构成，将提供以下多种功能。.q HBE-EMPOSIII-SV210 CPU Module 三星 S5PV210(ARM CortexTM-A8 Core) 512MByte DDR2 SDRAM : 128MByte * 4ea 256MByte NAND Flash Memory : 256MByte * 1eaq HBE-EMPOSIII-SV210 Base Board(CPU Connected) 10/100Base-T Ethernet Controller 7”TFT LCD with Touch Screen 3.1M Pixel CMOS Camera IIS Audio Codec : Speaker, MIC & Line-In USB 2.0 Host 3 Port and USB 2.0 OTG 1 Port RS232 Level UART 3 Port TTL Level UART 4 Port Bluetooth SD/MMC Card Connector 2 Port Composite Video Out 1 Port HDMI 1 Port SPDIF 1 Port 5 * 3 Keypad 1ea Jog Switch 1ea Power On/Off Switch 2ea Boot Mode Switchq HBE-EMPOSIII-SV210 Base Board(FPGA Connected) Character LCD(16 * 2) 1,3M Pixel CMOS Camera 6Digit 7-Segment 512Kbyte SRAM * 2ea 18,752 Logic Elements FPGA EP2C20 7 * 5 Dot Matrix 2ea 4 * 4 Keypad 8point DIP Switch 2ea OLED LED 8ea Buzzer Tact Switch 4ea Light Sensor Temperature/Humidity Sensor3.3 HBE-EMPOSIII-SV210 产品构成下显示了一套HBE-EMPOSIII-SV210产品中所包含的所有组件。. HBE-EMPOSIII-SV210 产品构成项目FeatureHBE-EMPOSIII-SV210Byte BlasterUSB 线(Mini to A Type)LAN 线(Straight)LAN 线(Crossover)并行数据线Serial 线电源线教材及产品 CD实验设备：PC 机和HBE-EMPOSIII-SV210实验箱各一台；实验步骤：1、对照阅读材料，在实验箱上找到CPU模块、FPGA模块、单片机模块；2、记录个模块主要的连接部件，主要的芯片型号；3、实验注意事项：本次实验无需打开实验箱电源。实验思考题：1、将下面材料翻译成中文，要求表达正确，专业术语表达恰当。（1）S5PV210 的特征如下。 ARM CortexTM-A8 based CPU Subsystem with NEON 32/32KB I/D Cache, 512KB L2 Cache Operating frequency up to 800 Mhz at 1.1V, 1 GHz at 1.2V 64-bit Multi-layer bus architecture MSYS domain for ARM CortexTM-A8, 3D engine, Multi Format Codec and Interrupt Controller Operating frequency up to 200 Mhz at 1.1V DSYS domain mainly for Display IPs(such as LCD controller, Camera interface, and TVout), and MDMA Operating frequency up to 166 Mhz at 1.1V PSYS domain mainly for other system component such as system peripherals,external memory interface, peri DMAs, connectivity IPs, and Audio interfaces. Operating frequency up to 133 Mhz at 1.1V Audio domain for low power audio play Advanced power management for mobile applications 64KB ROM for secure booting and 128KB RAM for security function 8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192 pixels for un-scaled resolution Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p30fps and coding of MPEG-2/VC1/Divx video up to 1080p30fps. JPEG codec support up to 80 Mpixels/s 3D Graphics Acceleration with programmable shader up to 20M triangles/s and 1000 Mpixels/s 2D Graphics Acceleration up to 160MPixels/s 1/2/4/8 bpp Palletized or 8/16/24bpp Non-Palletized Color-TFT recommended up to XGA resolution. TV-out and HDMI interface support for NTSC and PAL mode with image enhancer MIPI-DSI and MIPI-CSI interface One AC-97 audio codec interface and 3-channel PCM serial audio interface 3-channel 24-bit I2S interface 1-channel TX only S/PDIF interface support for digital audio 3-channel I2C interface 2-channel SPI interface 4-channel UART including 3Mbps port for Bluetooth 2.0 On-chip USB 2.0 OTG supporting high speed (480Mbps, on-chip transceiver) On-chip USB 2.0 Host Asynchronous Modem Interface 4 SD/SDIO/HS-MMC interface. ATA/ATAPI-6 standard interface 24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA) 14x8 key matrix interface 10-channel 12-bit multiplexed ADC Configurable GPIOs Real time clock, PLL, timer with PWM and watch dog timer. System timer support for accurate tick time in power down mode(except sleep mode) Memory Subsystem Asynchronous SRAM/ROM/NOR Interface with x8 or x16 data bus. NAND Interface with x8 data bus Muxed/Demuxed OneNAND Interface with x16 data bus. LPDDR1 Interface with x16 or x32 data bus (266400Mbps/pin DDR) DDR2 interface with x16 or x32 data bus (400Mbps/pin DDR) LPDDR2 interface (400Mbps/pin DDR)（2）系统特征q HBE-EMPOSIII-SV210 CPU Module 三星 S5PV210(ARM CortexTM-A8 Core) 512MByte DDR2 SDRAM : 128MByte * 4ea 256MByte NAND Flash Memory : 256MByte * 1eaq HBE-EMPOSIII-SV210 Base Board(CPU Connected) 10/100Base-T Ethernet Controller 7”TFT LCD with Touch Screen 3.1M Pixel CMOS Camera IIS Audio Codec : Speaker, MIC & Line-In USB 2.0 Host 3 Port and USB 2.0 OTG 1 Port RS232 Level UART 3 Port TTL Level UART 4 Port Bluetooth SD/MMC Card Connector 2 Port Composite Video Out 1 Port HDMI 1 Port SPDIF 1 Port 5 * 3 Keypad 1ea Jog Switch 1ea Power On/Off Switch 2ea Boot Mode Switchq HBE-EMPOSIII-SV210 Base Board(FPGA Connected) Character LCD(16 * 2) 1,3M Pixel CMOS Camera 6Digit 7-Segment 512Kbyte SRAM * 2ea 18,752 Logic Elements FPGA EP2C20 7 * 5 Dot Matrix 2ea 4 * 4 Keypad 8point DIP Switch 2ea OLED LED 8ea Buzzer Tact Switch 4ea Light Sensor Temperature/Humidity Sensor2、写出实验中记录的各模块主要的连接部件及主要的芯片型号，并简单描述各芯片的功能。CPU模块 SAMSUNG S5PV210AH ARM CortexTM-A8EM-S5PV210是一款功能极其强大的高端ARM Cortex-A8开发平台，其功能全面、接口丰富，完美展现了Samsuung S5PV210芯片的强大，主要面向企业用户进行产品开发过程中，对S5PV210芯片的性能评估、设计参考使用。其丰富的外设接口及强大的性能，也成为高校、科研机构等单位的最佳科研设备。EM-S5PV210开发板具有更高的主频和更丰富外设，能适用于对性能和处理能力有更高要求的嵌入式系统应用场合。FPGA模块 ALTERA cyclone11 EPEC20F484C8N K CBD9Y0937ACyclone II FPGA据称比上一代成本低30%，逻辑容量多三倍。 Cyclone II器件采用了TSMC验证的90nm低K介电质工艺制造的成本优化架构，容量从4,608至68,416个逻辑单元(LE)，是第一代Cyclone器件的三倍；同时，Cyclone II器件具有达150个嵌入1818乘法器，适合于实现低成本数字信号处理(DSP)应用，这些乘法器能运行至250MHz，消除了由复杂算法计算所导致的性能瓶颈，能用Cyclone II器件作为FPGA协处理器；此外 Cyclone II器件支持最近推出的Nios II系列嵌入式处理器，在Cyclone II器件中实现Nios II嵌入式处理器，能够在仅为0.35美元的逻辑上实现超过100DMIPS的性能。单片机模块 EMPOS III-SC1XX BASE ver 2.1提供具体支持第二题翻译的ARM CortexTM-A8与霓虹灯的CPU子系统32/32KB/ D缓存，512KB二级缓存1 GHz的工作频率高达800兆赫，在1.1V到1.2V64位多层总线架构MSYS的域名为ARM CortexTM-A8，3D引擎，多格式编解码器，中断控制器工作频率高达200 MHz在1.1VDSYS主要用于显示IP地址域（如LCD控制器，摄像头接口，TVOUT），亚甲二氧基甲基安非他明运行频率高达166兆赫，在1.1VPSYS域主要用于其他系统组件，如系统的外围设备，外部存储器接口，周围的DMA，连接的IP，和音频接口。工作频率高达133 MHz在1.1V域的低功耗音频播放音频用于移动应用的高级电源管理64KB ROM的安全引导和128KB RAM的安全功能8位ITU 601/656相机接口支持高达4224像素规模的联合国决议的规模和8192像素的横向尺寸多格式编解码器提供了编码和解码的MPEG-4/H.263/H.264 1080 30fps的MPEG-2/VC1/Divx视频编码的1080p 30fps的。JPEG编解码器，支持高达80万像素/秒可编程着色高达20M三角形/秒和1000万像素/秒的3D图形加速2D图形加速了到160MPixels / S建议1/2/4/8 bpp的托盘或无托盘8/16/24bpp彩色TFT XGA分辨率。电视输出和HDMI接口，支持NTSC和PAL模式与图像增强的MIPI-DSI和MIPI的CSI接口一