DSPBuilder的AM_2ASK2FSK信号调制的实现论文.doc

编号： EDA技术与Verilog HDL设计报告题 目： DSPBuilder的AM 2ASK 2FSK信号调制的实现 院 （系）： 计算机与控制学院 专 业： 控制理论与控制工程 学生姓名： 潘 鑫 龙 学 号： 112081205 同 作 者： 李 娇 指导教师： 潘 明 职 称： 副教授 题目类型： 理论研究 实验研究 工程设计 工程技术研究 软件开发2011 年 11 月 29 日 摘 要（内容采用小四号宋体）AM幅度调制信号发生器的设计是基于双DDS信号发生器以及乘法器混频的设计。本设计采用从Quatuse到MATLABSimulink的交互软件DSP_Building设计。所用的主要器件有：Constant、Input、Output、Bus Concatenation、AltBus、Adder、Delay、LUT、Multiplexer、Product、Bus Conversion、Signal Compiler、Scope（仿真器件）。其中调制信号由DDS信号源与调制度m相乘得到，并且通过信号上移保证调制波的单号性（全“+”），载波同样由另一路DDS信号发生器产生，并且其信号的频率为调制波信号的数倍（主要由DDS中的递增量决定）。将二者用乘法器调制为所需的AM波。对比2005年的电赛本设计，本设计扩展了2ASK和2FSK调制并且增加了原DDS输出，并且在设计中试用了不同的数据传输处理模式。最终完成Matlab和Quatuse的双仿真并下载仿真，经验证设计指标满足要求。关键词： AM调幅波、AM调制波、载波、混频、DDS信号发生器、多路选择器AbstractAM amplitude modulation signal generator design is based on dual DDS signal generator and the multiplier mixer design. This design uses the MATLAB-Simulink from Quatuse interactive software - DSP_Building design. The main components used are: Constant, Input, Output, Bus Concatenation, AltBus, Adder, Delay, LUT, Multiplexer, Product, Bus Conversion, Signal Compiler, Scope (emulation device). Which modulated signal from the DDS signal source and the modulation m multiplied, and modulated by the signal wave on the move to ensure that a single number of (full, ), the carrier the same way by another DDS signal generator, and the frequency of the signal modulated wave signal several times (mainly determined by the amount of increase in DDS). Multiplier will be used both for the desired AM modulation wave. Comparison, in 2005 the power game of the design, the design extends 2ASK and 2FSK modulation and increased raw DDS output, and the design of the trial in a different data processing mode. The final completion of the double-simulate Matlab and Quatuse and download simulation, proven design specifications to meet the requirements.Key words： AM amplitude modulation wave; AM modulation wave; carrier; mixing; DDS signal generator; multiplexer目 录引言41 实验原理52 DDS设计52.1 调制度m的设置72.2 AM调制的整体设计72.3 2ASK、2FSK调制的整体设计102.4 信号的功率谱及带宽102.4.1 2FSK信号的产生112.4.2 2FSK信号的调制方法113 设计编译下载143.1 singnal compiler153.2 QUARTUS2的编译、分配管脚、仿真、和设计154 设计注意事项175 结论19谢 辞20参考文献21附 录21附录1程序VHDL描述21引言 本次设计是基于Matlab的simulink功能和DSPBuilder来设计FPGA程序、 仿真以及下载仿真。基于DSPBuilder的设计再在Atera的设计平台Quartus上仿真和下载。 Altera可编程逻辑器件(PLD)中的DSP系统设计需要高级算法和HDL开发工具。Altera DSP Builder将The MathWorks MATLAB和Simulink系统级设计工具的算法开发、仿真和验证功能与VHDL综合、仿真和Altera开发工具整合在一起，实现了这些工具的集成。 DSP Builder在算法友好的开发环境中帮助设计人员生成DSP设计硬件表征，从而缩短了DSP设计周期。已有的MATLAB函数和Simulink模块可以和Altera DSP Builder模块以及Altera知识产权(IP)MegaCore功能相结合，将系统级设计实现和DSP算法开发相链接。DSP Builder支持系统、算法和硬件设计共享一个公共开发平台。 设计人员可以使用DSP Builder模块迅速生成Simulink系统建模硬件。DSP Builder包括比特和周期精度的Simulink模块，涵盖了算法和存储功能等基本操作。可以使用DSP Builder模型中的MegaCore功能实现复杂功能的集成。 Altera还提供DSP Builder高级模块集，这一Simulink库实现了时序驱动的Simulink综合。 Altera MegaCore是高级参数化IP功能，例如有限冲击响应(FIR)滤波器和快速傅立叶变换(FFT)等，经过配置能够迅速方便的达到系统性能要求。MegaCore功能支持Altera的IP评估特性，使您在购买许可之前，便可以验证功能及其时序。 Altera IP MegaStore网站上为DSP Builder和IP评估流程提供DSP IP完整介绍 DSP Builder SignalCompiler模块读取由DSP Builder和MegaCore模块构建的Simulink建模文件(.mdl)，生成VHDL文件和工具命令语言(Tcl)脚本，进行综合、硬件实施和仿真。图示为DSP Builder设计流程。 DSP Builder是一个系统级（或算法级）设计工具，它构架在多个软件工具之上，并把系统级和RTL级两个设计领域的设计工具连接起来，最大程度地发挥了两种工具的优势。DSP Builder依赖于Math Works公司的数学分析工具Matlab/Simulink，以Simulink的Blockset出现，可以在Simulink中进行图形化设计和仿真，同时又通过Signal Compiler可以把Matlab/Simulink的设计文件（.mdl）转成相应的硬件描述语言VHDL设计文件（.vhd）,以及用于控制综合与编译的TCL脚本。而对后者的处理可以由FPGA/CPLD开发工具Quartus II来完成。 1 实验原理 实验原理：AM幅度调制信号的函数表示为：来表述，f，f1，f2分别是调制后、载波和调制信号，m是调制度，0m Bus_Concatenation2:bsignal Bus_Concatenation9_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Bus_Concatenation9:output - Bus_Concatenation8:bsignal Delay_output_wire : STD_LOGIC_VECTOR(16 downto 0); - Delay:output - AltBus3:input, cast4:inputsignal Delay1_output_wire : STD_LOGIC_VECTOR(15 downto 0); - Delay1:output - AltBus7:input, cast5:inputsignal Input2_0_output_wire : STD_LOGIC_VECTOR(7 downto 0); - Input2_0:output - Bus_Concatenation9:asignal Input3_0_output_wire : STD_LOGIC_VECTOR(3 downto 0); - Input3_0:output - Bus_Concatenation1:asignal Input_0_output_wire : STD_LOGIC_VECTOR(2 downto 0); - Input_0:output - Multiplexer:selsignal Constant10_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant10:output - Multiplexer:in0signal Constant11_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant11:output - Multiplexer:in1signal Constant12_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant12:output - Multiplexer:in2signal Constant13_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant13:output - Multiplexer:in3signal Constant5_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant5:output - Multiplexer:in4signal Constant8_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant8:output - Multiplexer:in5signal Constant9_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant9:output - Multiplexer:in6signal Constant14_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant14:output - Multiplexer:in7signal Input5_0_output_wire : STD_LOGIC_VECTOR(0 downto 0); - Input5_0:output - Multiplexer1:sel, Multiplexer2:sel, cast26:inputsignal Constant20_output_wire : STD_LOGIC_VECTOR(0 downto 0); - Constant20:output - Multiplexer1:in0signal Constant21_output_wire : STD_LOGIC_VECTOR(0 downto 0); - Constant21:output - Multiplexer1:in1signal LUT2_Output_wire : STD_LOGIC_VECTOR(7 downto 0); - LUT2:Output - Output1_0:input, cast15:input, cast22:inputsignal LUT1_Output_wire : STD_LOGIC_VECTOR(7 downto 0); - LUT1:Output - Output2_0:input, cast17:input, cast19:inputsignal Pipelined_Adder1_result_wire : STD_LOGIC_VECTOR(16 downto 0); - Pipelined_Adder1:result - Delay:inputsignal AltBus7_output_wire : STD_LOGIC_VECTOR(15 downto 0); - AltBus7:output - Pipelined_Adder4:dataasignal Bus_Concatenation8_output_wire : STD_LOGIC_VECTOR(15 downto 0); - Bus_Concatenation8:output - Pipelined_Adder4:databsignal Pipelined_Adder4_result_wire : STD_LOGIC_VECTOR(15 downto 0); - Pipelined_Adder4:result - Delay1:inputsignal Pipelined_Adder2_result_wire : STD_LOGIC_VECTOR(8 downto 0); - Pipelined_Adder2:result - Product1:dataasignal Pipelined_Adder3_result_wire : STD_LOGIC_VECTOR(10 downto 0); - Pipelined_Adder3:result - Product2:dataa, cast14:inputsignal Pipelined_Adder6_result_wire : STD_LOGIC_VECTOR(8 downto 0); - Pipelined_Adder6:result - Product3:dataasignal Product3_result_wire : STD_LOGIC_VECTOR(17 downto 0); - Product3:result - Multiplexer2:in1signal Pipelined_Adder5_result_wire : STD_LOGIC_VECTOR(8 downto 0); - Pipelined_Adder5:result - Product4:dataasignal Product4_result_wire : STD_LOGIC_VECTOR(17 downto 0); - Product4:result - Multiplexer2:in0signal Constant1_output_wire : STD_LOGIC_VECTOR(7 downto 0); - Constant1:output - cast0:inputsignal cast0_output_wire : STD_LOGIC_VECTOR(0 downto 0); - cast0:output - Bus_Concatenation1:bsignal Constant3_output_wire : STD_LOGIC_VECTOR(7 downto 0); - Constant3:output - cast1:inputsignal cast1_output_wire : STD_LOGIC_VECTOR(10 downto 0); - cast1:output - Bus_Concatenation2:asignal Constant6_output_wire : STD_LOGIC_VECTOR(7 downto 0); - Constant6:output - cast2:inputsignal cast2_output_wire : STD_LOGIC_VECTOR(5 downto 0); - cast2:output - Bus_Concatenation8:asignal Constant7_output_wire : STD_LOGIC_VECTOR(7 downto 0); - Constant7:output - cast3:inputsignal cast3_output_wire : STD_LOGIC_VECTOR(1 downto 0); - cast3:output - Bus_Concatenation9:bsignal cast4_output_wire : STD_LOGIC_VECTOR(15 downto 0); - cast4:output - Bus_Conversion4:inputsignal cast5_output_wire : STD_LOGIC_VECTOR(15 downto 0); - cast5:output - Bus_Conversion1:inputsignal Bus_Conversion4_output_wire : STD_LOGIC_VECTOR(8 downto 0); - Bus_Conversion4:output - cast6:inputsignal cast6_output_wire : STD_LOGIC_VECTOR(7 downto 0); - cast6:output - LUT1:Inputsignal Bus_Conversion1_output_wire : STD_LOGIC_VECTOR(8 downto 0); - Bus_Conversion1:output - cast7:inputsignal cast7_output_wire : STD_LOGIC_VECTOR(7 downto 0); - cast7:output - LUT2:Inputsignal Multiplexer2_result_wire : STD_LOGIC_VECTOR(17 downto 0); - Multiplexer2:result - cast8:inputsignal cast8_output_wire : STD_LOGIC_VECTOR(7 downto 0); - cast8:output - Output5_0:inputsignal AltBus3_output_wire : STD_LOGIC_VECTOR(15 downto 0); - AltBus3:output - cast9:inputsignal cast9_output_wire : STD_LOGIC_VECTOR(16 downto 0); - cast9:output - Pipelined_Adder1:dataasignal Bus_Concatenation2_output_wire : STD_LOGIC_VECTOR(15 downto 0); - Bus_Concatenation2:output - cast10:inputsignal cast10_output_wire : STD_LOGIC_VECTOR(16 downto 0); - cast10:output - Pipelined_Adder1:databsignal Constant4_output_wire : STD_LOGIC_VECTOR(7 downto 0); - Constant4:output - cast11:inputsignal cast11_output_wire : STD_LOGIC_VECTOR(8 downto 0); - cast11:output - Pipelined_Adder2:databsignal Bus_Conversion2_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Bus_Conversion2:output - cast12:inputsignal cast12_output_wire : STD_LOGIC_VECTOR(10 downto 0); - cast12:output - Pipelined_Adder3:dataasignal Constant17_output_wire : STD_LOGIC_VECTOR(9 downto 0); - Constant17:output - cast13:inputsignal cast13_output_wire : STD_LOGIC_VECTOR(10 downto 0); - cast13:output - Pipelined_Adder3:databsignal cast14_output_wire : STD_LOGIC_VECTOR(10 downto 0); - cast14:output - Output_0:inputsignal cast15_output_wire : STD_LOGIC_VECTOR(8 downto 0); - cast15:output - Pipelined_Adder5:dataasignal Constant22_output_wire : STD_LOGIC_VECTOR(7 downto 0); - Constant22:output - cast16:inputsignal cast16_output_wire : STD_LOGIC_VECTOR(8 downto 0); - cast16:output - Pipelined_Adder5:databsignal cast17_output_wire : STD_LOGIC_VECTOR(8 downto 0); - cast17:output - Pipelined_Adder6:dataasignal Constant23_output_wire : STD_LOGIC_VECTOR(7 downto 0); - Constant23:output - cast18:inputsignal cast18_output_wire : STD_LOGIC_VECTOR(8 downto 0); - cast18:output - Pipelined_Adder6:databsignal cast19_output_wire : STD_LOGIC_VECTOR(15 downto 0); - cast19:output - Product:dataasignal Multiplexer_result_wire : STD_LOGIC_VECTOR(9 downto 0); - Multiplexer:result - cast20:inputsignal cast20_output_wire : STD_LOGIC_VECTOR(15 downto 0); - cast20:output - Product:databsignal Product_result_wire : STD_LOGIC_VECTOR(31 downto 0); - Product:result - cast21:inputsignal cast21_output_wire : STD_LOGIC_VECTOR(8 downto 0); - cast21:outpu