FPGA时钟显示QuartusⅡ程序代码.doc

-FPGA时钟显示Quartus程序代码-epm240芯片已验证可使用library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shzh isport(res:in std_logic; clk:in std_logic; dataout:out std_logic_vector(7 downto 0); en:out std_logic_vector(3 downto 0);end shzh;architecture arr of shzh issignal data1,data2,data3,data4,data_temp:std_logic_vector(3 downto 0);signal en_xhdl:std_logic_vector(3 downto 0);signal count:integer range 0 to 60000000;signal clk_data:std_logic;beginen=en_xhdl;process(clk,count)variable cnt_scan:std_logic_vector(15 downto 0);beginif clkevent and clk=1 thencnt_scan:=cnt_scan+1;if count=25000000 thencount=0;clk_data=not clk_data;else counten_xhdlen_xhdlen_xhdlen_xhdlnull;end case;end process;process(en_xhdl) begincase en_xhdl is when 1110= data_temp data_temp data_temp data_temp null;end case;end process;process(clk_data,res)begin if res=0 then data1=0000; data2=0000; data3=0000; data4=0000; elsif clk_dataevent and clk_data=1 then if data1=1001 then data1=0000; if data2=0101 then data2=0000; if data3=0011 and data4=0010 then data3=0000; data4=0000; elsif data3=1001 then data3=0000; data4=data4+1; else data3=data3+1; end if; elsedata2=data2+1; end if; else data1dataoutdataoutdataoutdataoutdataoutdataoutdataoutdataoutdataoutdataoutdataoutdataoutdataout