西安交大数电数字钟实验报告.doc

.西安交通大学数字电子技术实验报告数字钟设计姓名：*学院：*学院班级：*22学号：212*5 一、 实验名称基于Verilog HDL设计的多功能数字钟二、 试验任务及要求实验要求以Verilog HDL语言为手段，设计多功能数字钟。多功能数字钟应该具有的功能有：显示时分秒、整点报时、小时和分钟可调等基本功能。整个钟表的工作应该是在1Hz信号的作用下进行，这样每来一个时钟信号，秒增加1秒，当秒从59秒跳转到00秒时，分钟增加1分，同时当分钟从59分跳转到00分时，小时增加1小时，小时的范围为023时。在实验中为了显示与编写方便，该设计采用一个位24位二进制码23:0cnt记录时间，每四位记录一个数，从高到低分别为时针十位、时针个位、分针十位、分针个位、秒针十位、秒针个位。 实验中由于七段码管是扫描的方式显示，所以虽然时钟需要的是1Hz时钟信号，但是扫描需要一个比较高频率的信号，因此为了得到准确的1Hz信号，必须对输入的系统时钟50Mhz进行分频。关于调整时间功能，该设计采用四个按钮调整对应位的数值，从而调整时间。三、 实验条件该实验以Verilog HDL语言为手段，以Xilinx ISE Design Suite 13.4_1软件实现源程序的综合与仿真，并用BASYS2开发板作为目标器件。四、 设计过程1. 列写多功能数字钟设计-层次结构图2.拟定数字钟的组成框图，在Xilinx ISE Design Suite 13.4_1软件中，使用Verilog语言输入，采用分层次分模块的方法设计电路；3.设计各单元电路并进行仿真；4.对数字钟的整体逻辑电路图，选择器件，分配引脚，进行逻辑综合；5.下载到Basys2实验平台上，实际测试数字钟的逻辑功能。五、 Verilog代码module clock(input clk, input en, input key1, input key2, input key3, input key4, output sec, output wire7:0 seg, output wire3:0 digit );wire3:0 num0,mum1,num2,num3;disp u0(clk,num0,mum1,num2,num3,seg,digit);clk_gen u1(clk,en,key1,key2,key3,key4,sec,num0,mum1,num2,num3);endmodule/module disp(input clk, input 3:0 num0,input 3:0 num1,input 3:0 num2,input 3:0 num3,output reg7:0 sm_seg,output reg3:0 an);reg1:0 s;reg3:0 digit;reg16:0 clkdiv;always(*) begin an=4b1111; s=clkdiv16:15; ans=0; case(s) 0:digit=num0; 1:digit=num1; 2:digit=num2; 3:digit=num3; default:digit=num0; endcase case(digit) 4h0 : sm_seg = 8hc0; / 04h1 : sm_seg = 8hf9; / 14h2 : sm_seg = 8ha4; / 24h3 : sm_seg = 8hb0; / 34h4 : sm_seg = 8h99; / 44h5 : sm_seg = 8h92; / 54h6 : sm_seg = 8h82; / 64h7 : sm_seg = 8hf8; / 74h8 : sm_seg = 8h80; / 84h9 : sm_seg = 8h90; / 9default : sm_seg = 8hff; / xendcaseendalways(posedge clk)clkdiv=clkdiv+17d1;Endmodule/module clk_gen(input clk, input en,input bt0,input bt1,input bt2,input bt3,output reg sec,output 3:0 num0,output 3:0 num1,output 3:0 num2,output 3:0 num3);reg25:0 ctr;reg3:0 mytime3:0;reg7:0 s;assign num0=mytime0;assign num1=mytime1;assign num2=mytime2;assign num3=mytime3;always(posedge clk)beginctr=ctr+26d1;if(ctr=25000000-1)beginctr=0;sec=sec;endend/wire sen;/assign sen=(sec)|(bt0)|(bt1)|(bt2)|(bt3);always(negedge sec)if(!en)begin if(bt0) begin mytime0=mytime0+4d1; if(mytime0=9) mytime0=0; end else if(bt1) begin mytime1=mytime1+4d1; if(mytime1=5) mytime1=0; end else if(bt2) begin mytime2=mytime2+4d1; if(mytime2=9) mytime2=0; end else if(bt3) begin mytime3=mytime3+4d1; if(mytime3=2) mytime3=0; endendelsebegin s=s+1; if(s=59) begin s=0; mytime0=mytime0+4d1; if(mytime0=9) begin mytime0=0; mytime1=mytime1+4d1; if(mytime1=5) begin mytime1=0; mytime2=mytime2+4d1; if(mytime3=2 & mytime2=3) begin mytime2=0; mytime3=0; end if(mytime2=9) begin mytime2=0; mytime3=mytime3+4d1; end end endendendEndmodule约束文件NET clk LOC = B8; NETseg0 LOC=L14;NETseg1 LOC=H12;NETseg2 LOC=N14;NETseg3 LOC=N11;NETseg4 LOC=P12;NETseg5 LOC=L13;NETseg6 LOC=M12;NETseg7 LOC=N13;NET digit0 LOC = F12; NET digit1 LOC = J12; NET digit2 LOC = M13; NET digit3 LOC = K14;NET key4 LOC = A7; # Bank = 2, Signal name = BTN3NET key3 LOC = M4; # Bank = 2, Signal name = BTN2NET key2 LOC = C11; # Bank = 2, Signal name = BTN1NET key1 LOC = G12; # Bank = 2, Signal name = BTN0NET en LOC = P11; # Bank = 2, Signal name = sw0NET secLOC=M5;测试代码module clock(input clk, input en, input key1, input key2, input key3, input key4, output sec, output wire7:0 seg, output wire3:0 digit );wire3:0 num0,mum1,num2,num3;disp u0(clk,num0,mum1,num2,num3,seg,digit);clk_gen u1(clk,en,key1,key2,key3,key4,sec,num0,mum1,num2,num3);endmodule/module disp(input clk, input 3:0 num0,input 3:0 num1,input 3:0 num2,input 3:0 num3,output reg7:0 sm_seg,output reg3:0 an);reg1:0 s;reg3:0 digit;reg16:0 clkdiv;always(*) begin an=4b1111; s=clkdiv16:15; ans=0; case(s) 0:digit=num0; 1:digit=num1; 2:digit=num2; 3:digit=num3; default:digit=num0; endcase case(digit) 4h0 : sm_seg = 8hc0; / 04h1 : sm_seg = 8hf9; / 14h2 : sm_seg = 8ha4; / 24h3 : sm_seg = 8hb0; / 34h4 : sm_seg = 8h99; / 44h5 : sm_seg = 8h92; / 54h6 : sm_seg = 8h82; / 64h7 : sm_seg = 8hf8; / 74h8 : sm_seg = 8h80; / 84h9 : sm_seg = 8h90; / 9default : sm_seg = 8hff; / xendcaseendalways(posedge clk)clkdiv=clkdiv+17d1;Endmodule/module clk_gen(input clk, input en,input bt0,input bt1,input bt2,input bt3,output reg sec,output 3:0 num0,output 3:0 num1,output 3:0 num2,output 3:0 num3);reg25:0 ctr;reg3:0 mytime3:0;reg7:0 s;assign num0=mytime0;assign num1=mytime1;assign num2=mytime2;assign num3=mytime3;always(posedge clk)beginctr=ctr+26d1;if(ctr=25000000-1)beginctr=0;sec=sec;endend/wire sen;/assign sen=(sec)|(bt0)|(bt1)|(bt2)|(bt3);always(negedge sec)if(!en)begin if(bt0) begin mytime0=mytime0+4d1; if(mytime0=9) mytime0=0; end else if(bt1) begin mytime1=mytime1+4d1; if(mytime1=5) mytime1=0; end else if(bt2) begin mytime2=mytime2+4d1; if(mytime2=9) mytime2=0; end else if(bt3) begin mytime3=mytime3+4d1; if(mytime3=2) mytime3=0; endendelsebegin s=s+1; if(s=59) begin s=0; mytime0=mytime0+4d1; if(mytime0=9) begin mytime0=0; mytime1=mytime1+4d1; if(mytime1=5) begin mytime1=0; mytime2=mytime2+4d1; if(mytime3=2 & mytime2=3) begin mytime2=0; mytime3=0; end if(mytime2=9) begin mytime2=0; mytime3=mytime3+4d1; end end