用FPGA实现的七段数码管vhdl代码.doc

设计目的：根据四位（高电平）输入选择七段数码管的管脚输出（高电平）。Input(3 down to 0) Output(7 downto 0)设计分析：端口： 输入端口：Input(3 downto 0) 输出端口：Output(7 downto 0)功能： 输入4位组合2进制译码16进制数（高电平有效）， 由七段数码管对应引脚组合输出显示译码（高电平有效） 使用引脚：输出引脚:N19; N15; R20; R18; U20; T18; U18; W20;输入引脚F18; G20; J18; L18;具体设计： Vhd代码:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity sevenled_vhd is Port ( input : in STD_LOGIC_VECTOR (3 downto 0); led : out STD_LOGIC_VECTOR (7 downto 0);end sevenled_vhd;architecture Behavioral of sevenled_vhd isbeginled= 11000000 when input=0000 else - 0 11111001 when input=0001 else - 1 10100100 when input=0010 else - 2 10110000 when input=0011 else - 3 10011001 when input=0100 else - 4 10010010 when input=0101 else - 5 10000010 when input=0110 else - 6 11111000 when input=0111 else - 7 10000000 when input=1000 else - 8 10010000 when input=1001 else - 9 10001000 when input=1010 else - A 10000011 when input=1011 else - b 10100111 when input=1100 else - c 10100001 when input=1101 else - d 10000110 when input=1110 else - E 10001110; - Fend Behavioral;管脚约束: Net led LOC=N19;Net led LOC=N15;Net led LOC=R20;Net led LOC=R18;Net led LOC=U20;Net led LOC=T18;Net led LOC=U18;Net led LOC=W20;Net input LOC=F18;Net input LOC=G20;Net input LOC=J18;Net input LOC=L18; 综合结果: 仿真:wait for 100ms; -0input=0000;wait for 100ms; -1input=0001;wait for 100ms; -2input=0010;wait for 100ms; -3input=0011;wait for 100ms; -4input=0100;wait for 100ms; -5input=0101;wait for 100ms; -6input=0110;wait for 100ms; -7input=0111;wait for 100ms; -8input=1000;wait for 100ms; -9input=1001;wait for 100ms; -Ainput=1010;wait for 100ms; -Binput=1011;wait for 100ms; -Cinput=1100;wait for 100ms; -Dinput=1101;wa