verilog代码编写的coffee机.doc

自动售咖啡机1.客户需求只售咖啡三元一杯，接收硬币5角和1元不找零钱售货机中杯子永远用不完2.工作流程图3.数据通道4.控制单元 5.代码数据通道module datapath(equal,ld_sum,sel,clr,clk);/数据通道顶层output equal;input ld_sum,clr,clk,sel;wire1:0 M_A;wire2:0 A_R,R_C;mux m1(M_A,sel,1,2);/低电平选择1add m2(A_R,M_A,R_C);/r代表2位regs m3(R_C,A_R,clk,clr,ld_sum);compare m4(equal,R_C,6);/后面的常量endmodulemodule mux(out,sel,a,b);/数据选择器output1:0 out;input sel;input1:0a,b;reg 1:0 out;always(a or b or sel)beginif(!sel) out=a; else out=b;endendmodulemodule add(out,r,p);/加法器output 2:0 out;input 1:0 r;input 2:0 p;assign out=p+0,r;endmodulemodule regs(dout,din,clk,clr,ld);/寄存器output2:0 dout;input2:0 din;input clk,clr,ld;reg2:0 dout;always(posedge clk )beginif(clr) dout=0;else if(ld) dout=din; else dout=b)? 1:0;endmodule控制单元：module contrl(p_cup,i_coffe,ld_sum,sel,clr,reset,clk,c1,c2,equal,start,p_ready,i_ready);output p_cup,i_coffe,ld_sum,sel,clr;input clk,c1,c2,p_ready,i_ready,reset,start,equal;reg p_cup,i_coffe,ld_sum,sel,clr;reg3:0 present_state,next_state;parameter Idle=4b0000,Wait=4b0001,Add_a=4b0010,Add_b=4b0011,Place_cup=4b0100,Inject_coffe=4b0101,Clear_up=4b0110; always(posedge clk or negedge reset)beginif(!reset) present_state=Idle;else present_state=next_state;endalways(present_state or c1 or c2 or p_ready or i_ready or start)begin case(present_state)Idle:begin p_cup=0;i_coffe=0;ld_sum=0;sel=0;clr=1; if(!start) next_state=Idle; else next_state=Wait; endWait:begin p_cup=0;i_coffe=0;ld_sum=0;sel=0;clr=0;if(c2) next_state=Add_a; else if(c1) next_state=Add_b;else next_state=Wait; end Add_a:begin p_cup=0;i_coffe=0;ld_sum=1;sel=0;clr=0; next_state=Add_b; endAdd_b:begin p_cup=0;i_coffe=0;ld_sum=1;sel=0;clr=0;if(!equal) next_state=Wait;else next_state=Place_cup;endPlace_cup:begin p_cup=1;i_coffe=0;ld_sum=0;sel=0;clr=0;if(!p_ready) next_state=Place_cup; else next_state=Inject_coffe; end Inject_coffe:begin p_cup=0;i_coffe=1;ld_sum=0;sel=0;clr=0;if(!i_ready) next_state=Inject_coffe;else next_state=Clear_up; end Clear_up:begin p_cup=0;i_coffe=0;ld_sum=0;sel=0;clr=1;next_state=Wait; end endcaseendendmodulemodule coffe(P_cup,I_coffe,Clk,Reset,C1,C2,P_ready,I_ready,Start);/咖啡机顶层output P_cup,I_coffe;input Clk,Reset,C1,C2,P_ready,I_ready,Start;wire ld_sum,sel,clr,equal;contrl n1(P_cup,I_coffe,ld_sum,sel,clr,Reset,Clk,