乘法器电路的设计.ppt

9 2乘法器设计 应用数字信号处理和数字通信地位影响系统的运行速度实现并行乘法器移位相加乘法器查找表乘法器加法树乘法器 9 2 1并行乘法器 结构用乘法运算符描述由EDA软件综合优点运算速度快缺点耗用资源多 例9 4 8位并行乘法器modulemult outcome a b parametersize 8 input size 1 a b 源操作数output 2 size 1 outcome 乘积assignoutcome a b 相乘endmodule 8位并行乘法器RTL图 9 2 2移位相加乘法器 结构移位寄存器加法器优点耗用资源少 例9 16 8位二进制数的乘法modulemult for outcome a b parametersize 8 input size 1 a b output 2 size 1 outcome reg 2 size 1 outcome integeri always aorb beginoutcome 4 h0 for i 1 i size i i 1 if b i outcome outcome a i 1 endendmodule 乘法器的功能仿真波形图 9 2 3查找表乘法器 结构操作数 地址乘积 存储器优点运算速度快缺点耗用存储资源多 设计思路 4位查找表乘法器Y A BA A1 22 A2B B1 22 B2则Y A1 22 A2 B1 22 B2 A1 B1 24 A1 B2 22 A2 B1 22 A2 B2 8位查找表乘法器Y A BA A1 24 A2B B1 24 B2则Y A1 24 A2 B1 24 B2 A1 B1 28 A1 B2 24 A2 B1 24 A2 B2 例9 5 8 8查找表乘法器 2 2查找表乘法器 modulelookup out a b clk output 3 0 out 乘积input 1 0 a b 操作数inputclk reg 3 0 out reg 3 0 address 存储器地址 always posedgeclk beginaddress a b case address 4 h0 out 4 b0000 4 h1 out 4 b0000 4 h2 out 4 b0000 4 h3 out 4 b0000 4 h4 out 4 b0000 4 h5 out 4 b0001 4 h6 out 4 b0010 4 h7 out 4 b009 4 h8 out 4 b0000 4 h9 out 4 b0010 4 ha out 4 b0100 4 hb out 4 b090 4 hc out 4 b0000 4 hd out 4 b009 4 he out 4 b090 4 hf out 4 b1001 default out 4 bx endcaseendendmodule 4 4查找表乘法器 modulemult4x4 out a b clk output 7 0 out 乘积input 3 0 a b 操作数inputclk reg 7 0 out reg 1 0 firsta firstb 操作数高2位reg 1 0 seconda secondb 操作数低2位wire 3 0 outa outb outc outd 乘积每2位1组 always posedgeclk beginfirsta a 3 2 seconda a 1 0 firstb b 3 2 secondb b 1 0 end lookupm1 outa firsta firstb clk 元件调用m2 outb firsta secondb clk m3 outc seconda firstb clk m4 outd seconda secondb clk always posedgeclk beginout outa 4 outb 2 乘积 outc 2 outd endendmodule 4位查找表乘法器仿真波形图 8 8查找表乘法器 modulemult8x8 out a b clk output 15 0 out 乘积input 7 0 a b 操作数inputclk reg 15 0 out reg 3 0 firsta firstb 操作数高4位reg 3 0 seconda secondb 操作数低4位wire 7 0 outa outb outc outd 乘积每8位1组 always posedgeclk beginfirsta a 7 4 seconda a 3 0 firstb b 7 4 secondb b 3 0 end mult4x4n1 outa firsta firstb clk 元件调用n2 outb firsta secondb clk n3 outc seconda firstb clk n4 outd seconda secondb clk always posedgeclk beginout outa 8 outb 4 乘积 outc 4 outd endendmodule 8位查找表乘法器仿真波形图 9 2 4加法树乘法器 结构底层 乘法器高层 多级加法器优点1个时钟周期完成 加法树乘法器结构框图 例9 6 8位加法树乘法器moduleadd tree out a b clk output 15 0 out 乘积input 7 0 a b 操作数inputclk wire 15 0 out wire 15 0 out1 c1 加法器和wire 13 0 out2 wire 11 0 out3 c2 wire 9 0 out4 reg 14 0 temp0 最高位乘积reg 13 0 temp1 reg 12 0 temp2 reg 11 0 temp3 reg 10 0 temp4 reg 9 0 temp5 reg 8 0 temp6 reg 7 0 temp7 最低位乘积 8 1乘法器 function 7 0 mult8x1 input 7 0 operand inputsel beginmult8x1 sel operand 8 b00000000 endendfunction 操作数b各位与操作数a相乘 always posedgeclk begintemp7 mult8x1 a b 0 temp6 mult8x1 a b 1 1 temp5 mult8x1 a b 2 2 temp4 mult8x1 a b 3 3 temp3 mult8x1 a b 4 4 temp2 mult8x1 a b 5 5 temp1 mult8x1 a b 6 6 temp0 mult8x1 a b 7 7 end 加法器树运算 assignout1 temp0 temp1 assignout2 temp2 temp3 assignout3 temp4 temp5 assignout4 temp6 temp7 assignc1 out1 out2 assignc2 out3 out4 assignout c1 c2 endmodule 8位加法树乘法器仿真波形图 四种乘法器的比较 9 3乘累加器 MAC 的设计 例9 30 乘累加器 MAC moduleMAC out opa opb clk clr output 15 0 out input 7 0 opa opb inputclk clr wire 15 0 sum reg 15 0 out function 15 0 mult input 7 0 opa opb reg 15 0 result integeri beginresult opa 0 opb 0 for i 1 i 7 i i