Cadence高速电路解决方案.ppt

Cadence sSolutionforHigh SpeedDesign Agenda WhatisHigh SpeedDesign IdealHigh SpeedDesignProcessIntroductiontoSPECCTRAQuestPowerIntegritySPECCTRAQuestDemonstration TheDayof High Speed HasCome Pc boarddesigners meanwhile wereretoolingin1999forhigh speeddesign Signalintegrity onceconfinedtohigh endboards hasbecomeeverybody sproblem RichardGoering commentingonwhythePCBlayoutmarketgrew20 whiletheIClayoutmarketshrunk30 inEETimes4 10 2000page70 WelcomeNetworking HammerheadNetworks Agenda WhatisHigh SpeedDesign IdealHigh SpeedDesignProcessSPECCTRAQuestDemonstrationIntroductiontoSPECCTRAQuestPowerIntegrity NOW Whatis High Speed Over50MHzis High Speed High Speed isn trelatedtofrequency it safunctionofrisetimes Anetis High Speed whenitsround tripdelayisgreaterthantwiceitsedge speed Asignalis High Speed whenitisfasterthananythingyou vedesignedbefore High Speed occurswhenskineffectanddielectriclosseffectsbecomeimportant Huh Question Whichisa High Speed Problem Answer TheyBOTHAre DefinitionofHigh Speed Anetcanbeconsidered High Speed whenyouhavetodosomethingotherthansimplyconnectit High SpeedDesignInvolves2Things Netsthatareunderstood andmustbeconstrainedNetsthatmustbeanalyzedtobeunderstood andthenconstrained Netsthatareunderstood andmustbeconstrainedNetsthatmustbeanalyzedtobeunderstood andthenconstrained SDRAMDIMMLayout MODELS Datasheets Front sideBusSimulation MostToolsForceYoutoChoose GreatSimulator Analyze Constrain GreatLayoutSystem Hmm ButforHigh SpeedYouNeedBOTH AllinONEintegrated interactiveenvironment Let sGo SPECCTRAQuest IntegratedConstraint Analysis ModelDevelopment Verification TopologyEntry Floorplanning ConstraintDrivenLayout Analyze Constrain SPECCTRAQuesthelpsyoumanagetheprocessofHigh SpeedPCBdevelopmentthroughbothSimulationAnalysis Constraint DrivenLayouttasksACompleteSolution Pre RouteSol n SpaceAnalysis ExpandingExistingProcess PhysicalModelCreation Outline Floorplan RoomDef SchematicModelCreation SchematicCreation SCHEMATIC LAYOUT ToFinalVerification netlist SICleanRoute Back Annotate PCBRouting Agenda WhatisHigh SpeedDesign IdealHigh SpeedDesignProcessSPECCTRAQuestDemonstrationIntroductiontoSPECCTRAQuestPowerIntegrity NOW IdealHigh SpeedDesignFlow ModelDevelopment Verification TopologyEntry Floorplanning ConstraintDrivenLayout Analyze Constrain DevelopmentProcessFlow Pre RouteSol n SpaceAnalysis ModelDevelopment Verification NeedFlexibleDeviceModelingLanguage DML Today smodelscomeinmanystylesandformatsCadenceDMLcanmodelallformatsANDadvancedbehaviors forexample Merced Itanium QuadModels Package TransmissionLine Connector CableModels EBDModels CadenceDML can tdo M elementtoday IdealHigh SpeedDesignFlow ModelDevelopment Verification TopologyEntry Floorplanning ConstraintDrivenLayout Analyze Constrain DevelopmentProcessFlow Pre RouteSol n SpaceAnalysis Pre RouteSol n SpaceAnalysis Pre RouteSolutionSpaceAnalysis Exhaustive pre layout analysisofmanufacturinganddesignvariancesUsedtodefinetopologies routingrulesandterminationstrategiesCrosstalkanddatapatterndependenciesmaybetakenintoconsiderationSwept parameteranalysisisusedextensivelytocoverallcombinationsofconditionsNeedflexibilitytodefineanykindofsimulationandanykindofmeasurementcriteria Outputofpre layoutprocessisanelectronicconstraintfilethatcanbeusedtoguidethelayoutprocess Analyze TopologyTemplates DeriveandSave SolutionSpace Constrain IdealHigh SpeedDesignFlow ModelDevelopment Verification TopologyEntry Floorplanning ConstraintDrivenLayout Analyze Constrain DevelopmentProcessFlow Pre RouteSol n SpaceAnalysis TopologyEntry Floorplanning High SpeedPCBDesignNowRequiresBothElectronicInputstoFloorplanning Routing TopologyEntryandFloorplanning DesignrulesderivedfromsolutionspaceanalysisguidetheplacementprocessConstraintManagerspreadsheetsplaysakeyroleinguiding evaluatingcomponentplacementMargincolumnsshowdifferencebetweenconstraintanddesignvalueFastfeedbackColor codedstatus TopologyTemplates IdealHigh SpeedDesignFlow ModelDevelopment Verification TopologyEntry Floorplanning ConstraintDrivenLayout Analyze Constrain DevelopmentProcessFlow Pre RouteSol n SpaceAnalysis ConstraintDrivenLayout ConceptHDLCapture SPECCTRAQuestExploration SPECCTRAQuestFloorplanning Allegro APDLayout ConstraintManager Capture Exploration Floorplanning Layout GUI GUI GUI GUI Constraints Constraints Constraints Constraints ePlanner QUAD SPICE HyperLynx ViewDraw ICX Design BoardStation PADS VeriBest Architect ePlanner ConstraintManagementToday PSD14 0ConstraintManager Common powerfulenvironmentforconstraintentry editing managementandverificationSinglemechanismformanagingconstraintsthroughoutthedesignprocess ConstraintManager KeyFeatures Spreadsheet basedgraphicalinterfaceNocrypticformatsorcumbersomeupdatingProvidesunsurpassedIntegrationacrosstheentiredesignflowConsistentFronttoBacksolutionNomessytranslationswithstaticconstraintdataDirectlyintegratedwithschematicandPCBdatabasesAnalysisenginescanupdatespreadsheetdatainteractively ConstraintManager Hierarchy AllowsconstraintstobemanagedhierarchicallyGroupsofrulesaremaintainedasElectricalConstraintSets ECSets ProvidessinglepointforupdatingrulesorassigningtonetsECSetscanbeappliedtogroupsofnets buses withindividualoverrides ConstraintManager Systems SupportforsystemlevelconstraintsConstraintscanspanPCBboundaries TopologyTemplates ConstraintDrivenLayout Guides FloorplanningHandLayoutAuto Route ConstraintDrivenLayout Designruleviolationsduringinteractiveroutingareidentifiedinreal timeAutorouterfollowsdesignrules powerfulintegrationwithSPECCTRA Becausesolutionspaceanalysishasdefinedasetofconditionsunderwhichthenetsareknowntowork chanceoffirst passsuccessishigh Netscanberippedupandrerouted aslongastheystilladheretothedesignrules IdealHigh SpeedDesignFlow ModelDevelopment Verification TopologyEntry Floorplanning ConstraintDrivenLayout Analyze Constrain DevelopmentProcessFlow Pre RouteSol n SpaceAnalysis PostRouteAnalysisVerification Verification Agenda WhatisHigh SpeedDesign IdealHigh SpeedDesignProcessIntroductiontoSPECCTRAQuestPowerIntegritySPECCTRAQuestDemonstration NOW SPECCTRAQuestPowerIntegrityModule TheFutureofPowerDeliverySystemDesign SPECCTRAQuestPowerIntegrity InnovativetechnologydevelopedandprovenbySunMicrosystems nowcommercializedbyCadenceDesignSystems Inc toaddressPowerDeliveryissuesinhigh speedPCBSystemDesigns Adesigntool methodologyusedtodesignandoptimizethefrequency dependentcharacteristicsofPowerDeliverySystemsinhigh speedsystemdesignsAnintegratedsolutiontoallowmanyquickiterationsof change simulate analyze PowerDeliveryRequirementsTrend PowerdissipationandlongerbatterylifefuelingdecreasingchippowersupplyvoltagesMaximumallowablesupplyrippledecreasesaccordinglySoC SiPfuelingtrendtowardsdeviceswithlargenumberofdevicesTheinstantaneousswitchingcurrentrequiredisenormousThemaximumacceptablepowersupplyripplevoltagedeterminesthetargetimpedancewhichmustbemaintainedacrossthePCBMaximumsupplyimpedancemustbelessthan0 002Ohms PowerDeliverySystemDesignChallenges PowersupplydroopAlterssystemtimingandcancauseSetupfailuresCancausesamplingerrorsthatresultsinasystemcrashUnreliablepowerdeliverysystemdesigncancauseincreasedcommon modeEMIpreventingproductshipmentduetocomplianceproblemsPowerdeliverysystemimpedanceisfrequency dependentMustbecontrolledforallfrequencyrangeofalltransientcurrents IncreasesDevelopmentCostsandTimetoMarketisLOST PowerDeliverySystemDesign Howitisdonetoday StandaloneanalysistoolsDesigndatatranslationisleftuptotheuserChangestothedesignresultingfromsimulationismanualUseTimeDomainsimulationPowerdeliverysystemimpedanceisfrequency dependent Withonlytimedomainsimulation itislikesearchingforneedleinahaystackOverdesign addmorede couplingcapacitorsthannecessaryExpensivesolutionthatmaynotwork TheCadenceapproach AllowuserstodeterminetheneedsofthepowerdeliverysystemTargetimpedanceDecouplingcapacitorrequirementsProvidefrequencydomainanalysistofindproblemareasProvideanintegratedPCBdesigneditortooptimizecapacitorplacement Developreliablepowerdeliverysystemwhileshorteningdesigncycletime SPECCTRAQuestPowerIntegrity SoftwareComponents Frequency domainanalysisengineIntegratedPCBeditorthatincludesDecouplingcapacitorplacementenvironmentImpedancerequirementscalculatorDecouplingrequirementswizardHighspeedcapacitorlibrary libraryeditor IsolatingDecouplingProblemAreas DevicePlacement DecouplingCapacitors Capacitorscanbeselectedfromthedecoupling menu andplacedintothedesignTheeffectivedecouplingradiusisautomaticallydisplayedasthecapacitorispositionedDesignerscontinuetoadjustcapacitorselection placementuntilperformanceofthePDSisacceptable Allowsmany change simulate analyze cyclesinashorttime Release AvailablewithPSDreleaseversion14 1ScheduledforlateQ2 2001FirstreleaseavailableonSunSolaris 7 8 onlyOtherplatformstofollowwithnextmajorrelease SPECCTRAQuestPowerIntegrity Summary InnovativetechnologydevelopedandprovenbySunMicrosystems commercializedbyCadenceCombinedtoolsetandmethodologyforthedesignandanalysisofhighperformancepowerdeliverysystemsOfferedasanoptiontoSPECCTRAQuest integratedwithAllegroPartofCadence scompletefamilyofSignalIntegrity PowerDelivery EMIsolutions ShortensDevelopmentCycleandTimetoMarket Agenda WhatisHigh SpeedDesign IdealHigh SpeedDesignProcessIntroductiontoSPECCTRAQuestPowerIntegritySPECCTRAQuestDe