quartus-II-软件做4的位乘法器设计(vhdl-语言)

用 quartus II 软件设计 4 位乘法器 1 并行乘法的算法 下面根据乘法例题来分析这种算法 题中 M4 M3 M2 M1 是被乘数 用 M 表示 N4 N3 N2 N1 是乘数 用 N 表示 2 乘法模块 Library ieee Use ieee std logic 1164 all Use ieee std logic unsigned all Entity and4a is Port a in std logic vector 3 downto 0 en in std logic r out std logic vector 3 downto 0 End and4a Architecture behave of and4a is Begin Process en a 3 downto 0 Begin If en 1 then r a Else r 0000 End if End process End behave 3 加法模块 Library ieee Use ieee std logic 1164 all Use ieee std logic unsigned all Entity ls283 is Port o1 o2 in std logic vector 3 downto 0 res out std logic vector 4 downto 0 End ls283 Architecture behave of ls283 is Begin Process o1 o2 Begin res 0 End process End behave 4 主程序 Library ieee Use ieee std logic 1164 all Use ieee std logic unsigned all Entity mul4p is Port op1 op2 in std logic vector 3 downto 0 result out std logic vector 7 downto 0 End mul4p Architecture count of mul4p is component and4a port a in std logic vector 3 downto 0 en in std logic r out std logic vector 3 downto 0 End component Component ls283 port o1 o2 in std logic vector 3 downto 0 res out std logic vector 4 downto 0 End component Signal sa std logic vector 3 downto 0 Signal sb std logic vector 4 downto 0 Signal sc std logic vector 3 downto 0 Signal sd std logic vector 4 downto 0 Signal se std logic vector 3 downto 0 Signal sf std logic vector 3 downto 0 Signal sg std logic vector 3 downto 0 signal tmp1 std logic Begin sg 0 tmp1op2 en op1 1 r se U1 and4a port map a op2 en op1 3 r sa U2 ls283 port map o1 sb 4 downto 1 o2 sa res result 7 downto 3 U3 and4a port map a op2 en op1 2 r sc U4 ls283 port map o1 sc o2 sd 4 downto 1 res sb u5 ls283 port map o1 sg o2 se res sd u6 and4a port map a op2 en op1 0 r sf result 0 sf 0 result 1 sd 0 result 2 sb 0 result 7 downto 0 00000000 End count 5 仿真波形图 6 引脚分配图 7 硬件下载编程与硬件实现 在实现硬件测试