24进制计数器的2进制表示和8421BCD码表示

用 VHDL 语言描述一个 24 进制的计数器电路 1 要求输出计数值用二进制数表示 2 要求输出计数值用 8421BCD 码表示 输出计数值用二进制数表示 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY ersijinzhi IS PORT CLK RST EN IN STD LOGIC CQ OUT STD LOGIC VECTOR 4 DOWNTO 0 END ersijinzhi ARCHITECTURE ERJINZHI OF ersijinzhi IS BEGIN PROCESS CLK RST VARIABLE CQI STD LOGIC VECTOR 4 DOWNTO 0 BEGIN IF RST 1 THEN CQI OTHERS 0 ELSIF CLK EVENT AND CLK 1 THEN IF EN 1 THEN IF CQI 0 END IF END IF END IF CQ CQI END PROCESS END ERJINZHI 输出计数值用 8421BCD 码表示 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL USE IEEE STD LOGIC ARITH ALL ENTITY ersijinzhibcd IS PORT CLK RST IN STD LOGIC EN IN STD LOGIC LOW OUT STD LOGIC VECTOR 3 DOWNTO 0 HIGH OUT STD LOGIC VECTOR 3 DOWNTO 0 END ersijinzhibcd ARCHITECTURE rtl of ersijinzhibcd IS SIGNAL LOW REG STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL HIGH REG STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL CLR STD LOGIC 0 BEGIN 个位计数 LOW PROC PROCESS CLK EN CLR BEGIN IF RST 1 THEN LOW REG 0 ELSIF CLK EVENT AND CLK 1 THEN IF EN 1 THEN IF LOW REG 9 OR CLR 1 THEN LOW REG 0 ELSE LOW REG LOW REG 1 END IF END IF END IF END PROCESS LOW LOW REG 十位计数 HIGH PROC PROCESS CLK EN CLR BEGIN IF RST 1 THEN HIGH REG 0 ELSIF CLK EVENT AND CLK 1 THEN IF EN 1 THEN IF CLR 1 THEN HIGH REG 0 ELSIF LOW REG 9 THEN HIGH REG HIGH REG 1 END IF END IF END IF END PR