中山大学软件学院专业课计算机组成原理课件第10章

Chapter9andChapter118088 80286MicroprocessorsandISABusI OandThe8255 ISABusInterfacing MainContents Statethefunctionofthepinsofthe8088Listthefunctionsofthe8088data address andcontrolbusesStatethedifferencesinthe8088microprocessorinmaximummodeversusminimummodesExplainhowbusarbitrationbetweentheCPUandDMAisaccomplished StatethefunctionofI OportsReadandwritedatatoandfromI OportsDesignofperipheralI Ousingthe74LS373outputlatchandthe74LS244inputbufferI Oaddressmapof80 x86PCsThepurposeofthe8255chipCodeAssemblylanguageinstructionstoperformI Othroughthe8255 MainContents Sec 9 18088Microprocessor 8088Microprocessor ThefirstIBMPCusedthe8088microprocessor andmodernPCsstillcarrythatlegacy The8088isinternallyidenticaltothe8086 buthasonlyan8 bitexternaldatabus The8088isa40 pinmicroprocessorthatcanworkintwomodes minimummodeandmaximummode Maximummodeisusedwhenweneedtoconnectthe8088toan8087mathcoprocessor Sec 9 18088Microprocessor Databusin8088 Sec 9 18088Microprocessor Databusin8088 8088has8 bitexternaldatabus pins9 16 AD0 AD7 areusedforbothdataandaddresses Atthetimeofdesignofthismicroprocessorinthelate1970s duetoICchippackaginglimitations therewasagreatefforttousetheminimumnumberofpinsforexternalconnections Sec 9 18088Microprocessor Databusin8088 TheALEpinsignalswhethertheinformationonpinsAD0 AD7isaddressordata WhenALE 1 itindicatethattheinformationonthepinsAD0 AD7istheaddress A0 A7 WhenALE 0 itindicatethattheinformationonthepinsAD0 AD7isthedata D0 D7 Sec 9 18088Microprocessor Addressbusin8088 The8088has20addresspins A0 A19 allowingittoaddressamaximumofonemegabyteofmemory 1M PinsAD0 AD7providetheA0 A7addresseswiththeassistanceofalatch Todemultiplextheaddresssignalsfromtheaddress datapins alatchmustbeusedtograbtheaddresses Sec 9 18088Microprocessor Addressbusin8088 Sec 9 18088Microprocessor Addressbusin8088 A19 S6 A16 S3Theaddress databusbitsaremultiplexedtoprovideaddresssignalsA19 A16andalsostatusbitsS6 S3 StatusbitS6isalwaysalogic0 bitS5indicatestheconditionofIFflagbit andS4andS3showwhichsegmentisaccessedduringthecurrentbuscycle Sec 9 18088Microprocessor Addressbusin8088 Sec 9 18088Microprocessor 8088Controlbus Readingandwriting The8088canaccessbothmemoryandI Odevicesforreadandwriteoperations Thisgivesusfouroperationsforwhichweneedfourcontrolsignals MEMR memoryread MEMW memorywrite IOR I Oread andIOW I Owrite Thefourcontrolsignalsarerelativetothreepins Sec 9 18088Microprocessor 8088Controlbus Sec 9 18088Microprocessor 8088Controlbus Sec 9 18088Microprocessor Bustimingof8088 Theclockfrequencyis5MHzin8088 sotheperiodofclockcycleis200ns InIBMPC theclockfrequencyis4 77MHz sotheperiodofclockcycleis210ns Thebasicbuscyclein8088includes4clockcycles Sec 9 18088Microprocessor Bustimingof8088 InFigure9 6thetimingforALEisshown The8088uses4clocksformemoryandI Obusactivities Sec 9 18088Microprocessor Other8088pins Pins24 32ofthe8088havedifferentfunctionsdependingonwhetherthe8088isusedinminimummodeormaximummode Asstatedearlier maximummodeisusedonlywhenwewanttoconnectthe8088toan8087mathcoprocessor Table9 2liststhefunctionsofpins24 32ofthe8088inminimummode Sec 9 18088Microprocessor Other8088pins INTA interruptacknowledge Active lowoutputsignal ALE addresslatchenable Active highoutputsignal DEN dataenable Active lowoutputsignal DT R datatransmit receive outputsignal Active lowindicatesCPUreceivesdata Active highindicatesCPUsendsdata IO M input outputormemory indicateswhetheraddressbusisaccessingmemoryorIOdevice WR write Active low outputsignalRD read Active low outputsignalHOLD Active highinputsignalfromDMA HLDA holdacknowledge Active highoutputsignal Sec 9 18088Microprocessor Other8088pins MN MX minimum maximum Active lowindicatemaximummode NMI nonmaskableinterrupt thisisaedge triggered goingfromlowtohigh inputsignal INTR interruptrequest Active highinputsignal CLOCK Clockisaninputsignalandisconnectedto8284clockgenerator Ready isaninputsignalusedtoinsertawaitstateforslowermemoriesandI O TEST Inmaximummode isaninputfromthe8087 RESET toterminatethepresentactivitiesofthemicroprocessor Active high inputsignalSS0 isequivalenttotheS0pininmaximummode Sec 9 18088Microprocessor IPandSegmentregisterContentsafterReset Sec 11 18088Input Outputinstructions All80 x86microprocessors fromthe8088tothePentium canaccessexternaldevicescalledports ThisisdoneusingI Oinstructions The80 x86CPUisoneofthefewprocessorsthathaveI Ospaceinadditiontomemoryspace Therearetwoinstructionsforthispurpose OUT and IN Theseinstructionscansenddatafromtheaccumulator ALorAX toportsorbringdatafromportsintotheaccumulator Sec 11 18088Input Outputinstructions Oneexternaldevicecanhaveseveralports eachdevicehasthreetypesinformation control status data Eachtypeinformationmayoccupyoneorseveralports TheaddressingofCPUisport notactualdevice Sec 11 18088Input Outputinstructions The8 bitportusestheD0 D7databustocommunicatewithI Odevices In8 bitportprogramming RegisterALisused The8 bitportaddressiscarriedonaddressbusA0 A7 upto256ports The16 bitportaddressiscarriedonaddressbusA0 A15 upto65536ports Sec 11 18088Input Outputinstructions 8 bitdataports InstructionsOUTandINhavethefollowingformats InputtingDataOutputtingDataFormat INdest sourceOUTdest sourceINAL port OUTport ALMOVDX port MOVDX port INAL DXOUTDX AL Sec 11 18088Input Outputinstructions HowtouseI Oinstructions Thefollowingprogramsendsabyteofdatatoafixedportaddressof43H MOVAL 36HOUT43H ALTousethe16 bitportaddress registerindirectaddressingmodemustbeused BACK MOVDX 300HMOVAL 55HOUTDX ALMOVAL 0AAHOUTDX ALJMPBACK Sec 11 2I OAddressdecodinganddesign Themainpurposeofaddressdecodingistochoosetheexternaldevice soCPUcancommunicatewiththeappointeddevice WhenCPUcommunicateswiththeexternaldevice thereareseveralproblems 1 Thespeeddonotmatch CPUrunsfasterthanexternaldevice 2 ThecontrolanddatabusofexternaldevicecannotconnectwiththedataandcontrolbusofCPUdirectly 3 Theformatofdatainexternaldevicesaredifferent Sec 11 2I OAddressdecodinganddesign Ineverycomputer wheneverdataissentoutbytheCPUviathedatabus thedatamustbelatchedbythereceivingdevice Thewidelyusedchipis74LS373 Whendataiscominginbywayofadatabus itmustcomeinthroughathree statebuffer Thewidelyusedchipis74LS244 Sec 11 2I OAddressdecodinganddesign Theaddressbusdecodinghasthefollowingsteps 1 ThecontrolsignalsIORandIOWareusedalongwiththedecoder 2 Foran8 bitportaddress A0 A7isdecoded 3 Iftheportaddressis16 bit usingDX A0 A15isdecoded Sec 11 2I OAddressdecodinganddesign Usingthe74LS373inanoutputportdesign Whilememorieshaveaninternallatchtograbthedata alatchingsystemmustbedesignedforsimpleI Oports Inordertomake74lS373workasalatch theOCpinmustbegrounded Foranoutputlatch itiscommontoANDtheoutputoftheaddressdecoderwiththecontrolsignalIOWtoprovidethelatchingaction Sec 11 2I OAddressdecodinganddesign Usingthe74LS373inanoutputportdesign Sec 11 2I OAddressdecodinganddesign INportdesignusingthe74LS244 Sec 11 2I OAddressdecodinganddesign INportdesignusingthe74LS244 Forthesimpleinputportsweuse74LS244chiptobethetri statebuffer G1andG2eachcontrolonly4bitsofthe74LS244 theybothmustbeactivatedforthe8 bitinput TheaddressdecodingsignalAndedwiththeIORtoactivatetheGpinof74LS244 The74LS244notonlyplaystheroleofbuffer butalsoprovidestheincomingdatawithsufficientdrivingcapabilitytotravelallthewaytotheCPU Sec 11 2I OAddressdecodinganddesign INportdesignusingthe74LS244 Sec 11 2I OAddressdecodinganddesign MemoryMappedI O TherearetwotypesofI O oneisperipheralI O theotherismemory mappedI O ThemicroprocessorcommunicateswithI OdevicesusingINorOUTinstructionsinperipheralI O Inmemory mappedI O amemorylocationisassignedtobeinputoroutputport Sec 11 2I OAddressdecodinganddesign ThedifferencebetweenMemoryMappedI OandPeripheralI O Inmemory mappedI O wemustuseinstructionsaccessingmemorylocationstoaccesstheI OportsinsteadofINandOUTinstructions Inmemory mappedI O theentire20 bitaddress A0 A19 mustbedecoded Inmemory mappedI Ocircuitinterfacing controlsignalsMEMRandMEMWareused InperipheralI Owearelimitedto65536ports Inmemory mappedI O thenumberofportscanbe1048576 220 Inmemory mappedI O onecanperformarithmeticandlogicoperationsonI Odatadirectly Onemajorandseveredisadvantageofmemory mappedI Oisthatitusesmemoryaddressspace whichcouldleadtomemoryspacefragmentation Sec 11 3I OAddressmapofX86PCs DesignersoftheoriginalIBMPCassigneddifferentportaddressestovariousperipheralssuchasLPTandCOMports ThelistofthedesignatedI OportaddressesisreferredtoastheI Omap TheI Oaddress300 31Fhavenotbeenusedbythedesigners theyarecalledprototypecard wecanuseit Sec 11 3I OAddressmapofX86PCs Sec 11 3I OAddressmapofX86PCs Indecodingaddresses eitherallofthemoraselectednumberofthemaredecoded Ifalltheaddresslines A0 A15 aredecoded itiscalledabsolutedecoding Ifonlyselectedaddresspins A0 A9 areusedfordecoding itiscalledlinearselectdecoding Absolutevs linearselectaddressdecoding Sec 11 3I OAddressmapofX86PCs Inthex86PC theaddressrange300H 31FHissetasideforprototypecardstobepluggedintotheexpansionslot Itusesthefollowingsignals 1 IORandIOW bothareactivelow 2 AENsignal AEN 0whentheCPUisusingthebus 3 A0 A9foraddressdecoding Prototypeaddresses300 31FHinx86PC Sec 11 3I OAddressmapofX86PCs Useofsimplelogicgatesasaddressdecoders Sec 11 3I OAddressmapofX86PCs Useof74LS138asdecoder Sec 11 3I OAddressmapofX86PCs Useof74LS138asdecoder Sec 11 3I OAddressmapofX86PCs Port61Handtimedelaygeneration I Oportshaseightbits D0 D7 bitD4isofparticularinteresttous Inall286andhigherPCs bitD4ofport61Hchangesitsstateevery15 085microseconds s Itstayslowfor15 85 s thenchangestohighandstayshighforthesameamountoftimebeforeitgoeslowagain Sec 11 3I OAddressmapofX86PCs Port61Handtimedelaygeneration Togglingallbitsofport310Hevery0 5secMOVDX 310HHERE MOVAL 55HMOVCX 33144 Delay 33144 15 085us 0 5secCALLTDELAYMOVAL 0AAHOUTDX ALMOVCX 33144CALLTDLAYJMPHERE Sec 11 3I OAddressmapofX86PCs Port61Handtimedelaygeneration CX COUNTOF15 085MICROSECTDLAYPROCNEARPUSHAXW1 INAL 61HANDAL 00010000BCMPAL AHJEW1MOVAH ALLOOPW1POPAXRETTDLAYENDP Sec 11 48255PPIchip 8255chipisoneofthemostwidelyusedI Ochips Itisa40 pinDIPchip hasthreeseparatelyaccessibleports A B C whichcanbeprogrammed SoitiscalledPPI programmableperipheralinterface Theycanbechangeddynamically Sec 11 48255PPIchip Sec 11 48255PPIchip PortA PA0 PA7 canbeprogrammedallasinputorallasoutput PortB PB0 PB7 canbeprogrammedallasinputorallasoutput PortC PC0 PC7 canbeprogrammedallasinputorallasoutput itcanalsobesplitintotwoparts CU upperbitsPC4 PC7 andCL lowerbitsPC0 PC3 Eachcanbeusedforinputoroutput AnyofPC0toPC7canbeprogrammedindividually Sec 11 48255PPIchip 8255hasacontrolregister whichmustbeprogrammedtoselecttheoperationmodeofthethreeportsA B andC A0 A1 andCSCSselectstheentirechip AddresspinsA0andA1selectthespecificportwithinthe8255 ThesethreepinsareusedtoaccessportsA B Corthecontrolregister Sec 11 48255PPIchip 8255PortSelection Sec 11 48255PPIchip RDandWRThesetwoactive lowcontrolsignalsareinputtothe8255 RESETThisisanactive highsignalinputintothe8255usedtoclearthecontrolregister WhenRESETisactivated allportsareinitializedasinputports ThispinmustbeconnectedtotheRESEToutputofthesystembusorground D0 D7D0 D7areconnectedtosystemdatabus Thereisadatabufferin8255 usedtoconnecttosystemdatabus Sec 11 48255PPIchip Modeselectionofthe8255A Sec 11 48255PPIchip Modeselectionofthe8255A Theportsofthe8255canbeprogrammedinanyofthefollowingmodes Mode0 simpleI Omode Mode1 PortAandPortBcanbeusedasinputoroutputportswithhandshakingcapabilities Mode2 PortAcanbeusedasabidirectionalI O Sec 11 48255PPIchip Mode0Operation Inthismode anyoftheportsA B CL andCUcanbeprogrammedasinputoroutput Inthismode allbitsareoutorallarein Thereisnocontrolofindividualbits Mode0operationcauses8255tofunctioneitherasabufferedinputorasalatchedoutputdevice Mode0ismostwidelyusedmodeincurrentsystemI Ointerfacingdesign Sec 11 48255PPIchip BSR Bitssetorreset Sec 11 48255PPIchip BSR Bitssetorreset Theaddressof8255is320H 323HMOVAL 0FH SetPC7 1MOVDX 323HOUTDX ALMOVAL 06H SetPC3 0OUTDX AL Sec 11 48255PPIchip Example11 5The8255showninFigure11 13isconfiguredasfollows portAasinput Basoutput andallthebitsofportCasoutput FindtheportaddressesassignedtoA B Candthecontrolregisters Findthecontrolbyte word forthisconfiguration ProgramtheportstoinputdatafromportAandsendittobothportsBandC Sec 11 48255PPIchip Example11 5Solution Theportaddressesareasfollows CSA1A0AddressPort1100010000310HPortA1100010001311HPortB1100010010312HPortC1100010011313HControlregister b Thecontrolwordis90H or10010000 c Oneversionoftheprogramisasfollows MOVAL 90H controlbytePA in PB out PC outMOVDX 313HOUTDX ALMOVDX 310HINAL DXMOVDX 311HMOVDX 312HOUTDX ALOUTDX AL Sec 11 48255PPI