文献翻译——AT89C51

第1页外文文献资料TheGeneralSituationofAT89C511.TheapplicationofAT89C51Microcontrollersareusedinamultitudeofcommercialapplicationssuchasmodems,motor-controlsystems,airconditionercontrolsystems,automotiveengineandamongothers.Thehighprocessingspeedandenhancedperipheralsetofthesemicrocontrollersmakethemsuitableforsuchhigh-speedevent-basedapplications.However,thesecriticalapplicationdomainsalsorequirethatthesemicrocontrollersarehighlyreliable.Thehighreliabilityandlowmarketriskscanbeensuredbyarobusttestingprocessandapropertoolsenvironmentforthevalidationofthesemicrocontrollersbothatthecomponentandatthesystemlevel.IntelPlaformEngineeringdepartmentdevelopedanobject-orientedmulti-threadedtestenvironmentforthevalidationofitsAT89C51automotivemicrocontrollers.ThegoalsofthisenvironmentwasnotonlytoprovidearobusttestingenvironmentfortheAT89C51automotivemicrocontrollers,buttodevelopanenvironmentwhichcanbeeasilyextendedandreusedforthevalidationofseveralotherfuturemicrocontrollers.TheenvironmentwasdevelopedinconjunctionwithMicrosoftFoundationClasses(AT89C51).Thepaperdescribesthedesignandmechanismofthistestenvironment,itsinteractionswithvarioushardware/softwareenvironmentalcomponents,andhowtouseAT89C51.1.1.IntroductionThe8-bitAT89C51CHMOSmicrocontrollersaredesignedtohandlehigh-speedcalculationsandfastinput/outputoperations.MCS51microcontrollersaretypicallyusedforhigh-speedeventcontrolsystems.Commercialapplicationsincludemodems,motor-controlsystems,printers,photocopiers,airconditionercontrolsystems,diskdrives,andmedicalinstruments.The第2页automotiveindustryuseMCS51microcontrollersinengine-controlsystems,airbags,suspensionsystems,andantilockbrakingsystems(ABS).TheAT89C51isespeciallywellsuitedtoapplicationsthatbenefitfromitsprocessingspeedandenhancedon-chipperipheralfunctionsset,suchasautomotivepower-traincontrol,vehicledynamicsuspension,antilockbraking,andstabilitycontrolapplications.Becauseofthesecriticalapplications,themarketrequiresareliablecost-effectivecontrollerwithalowinterruptlatencyresponse,abilitytoservicethehighnumberoftimeandeventdrivenintegratedperipheralsneededinrealtimeapplications,andaCPUwithaboveaverageprocessingpowerinasinglepackage.Thefinancialandlegalriskofhavingdevicesthatoperateunpredictablyisveryhigh.Onceinthemarket,particularlyinmissioncriticalapplicationssuchasanautopilotoranti-lockbrakingsystem,mistakesarefinanciallyprohibitive.Redesigncostscanrunashighasa$500K,muchmoreifthefixmeans2backannotatingitacrossaproductfamilythatsharethesamecoreand/orperipheraldesignflaw.Inaddition,fieldreplacementsofcomponentsisextremelyexpensive,asthedevicesaretypicallysealedinmoduleswithatotalvalueseveraltimesthatofthecomponent.Tomitigatetheseproblems,itisessentialthatcomprehensivetestingofthecontrollersbecarriedoutatboththecomponentlevelandsystemlevelunderworstcaseenvironmentalandvoltageconditions.Thiscompleteandthoroughvalidationnecessitatesnotonlyawell-definedprocessbutalsoaproperenvironmentandtoolstofacilitateandexecutethemissionsuccessfully.IntelChandlerPlatformEngineeringgroupprovidespostsiliconsystemvalidation(SV)ofvariousmicro-controllersandprocessors.Thesystemvalidationprocesscanbebrokenintothreemajorparts.Thetypeofthedeviceanditsapplicationrequirementsdeterminewhichtypesoftestingareperformedonthedevice.1.2.TheAT89C51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afulldupleser-ialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequency第3页andsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsys-temtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscillatordisablingallotherchipfunctionsuntilthenexthardwarereset.Figure1-2-1BlockDiagram1.3.PinDescriptionThe8-bitAT89C51CHMOSmicrocontrollersaredesignedtohandlehigh-speedcalculationsandfastinput/outputoperations.MCS51microcontrollersaretypicallyusedforhigh-speedeventcontrolsystems.Commercialapplicationsincludemodems,motor-controlsystems,printers,photocopiers,airconditionercontrolsystems,diskdrives,andmedicalinstruments.TheautomotiveindustryuseMCS51microcontrollersinengine-controlsystems,airbags,suspensionsystems,andantilockbrakingsystems(ABS).TheAT89C51isespeciallywellsuitedtoapplicationsthatbenefitfromitsprocessing第4页speedandenhancedon-chipperipheralfunctionsset,suchasautomotivepower-traincontrol,vehicledynamicsuspension,antilockbraking,andstabilitycontrolapplications.Becauseofthesecriticalapplications,themarketrequiresareliablecost-effectivecontrollerwithalowinterruptlatencyresponse,abilitytoservicethehighnumberoftimeandeventdrivenintegratedperipheralsneededinrealtimeapplications,andaCPUwithaboveaverageprocessingpowerinasinglepackage.Thefinancialandlegalriskofhavingdevicesthatoperateunpredictablyisveryhigh.Onceinthemarket,particularlyinmissioncriticalapplicationssuchasanautopilotoranti-lockbrakingsystem,mistakesarefinanciallyprohibitive.Redesigncostscanrunashighasa$500K,muchmoreifthefixmeansbackannotatingitacrossaproductfamilythatsharethesamecoreand/orperipheraldesignflaw.Inaddition,fieldreplacementsofcomponentsisextremelyexpensive,asthedevicesaretypicallysealedinmoduleswithatotalvalueseveraltimesthatofthecomponent.Tomitigatetheseproblems,itisessentialthatcomprehensivetestingofthecontrollersbecarriedoutatboththecomponentlevelandsystemlevelunderworstcaseenvironmentalandvoltageconditions.Thiscompleteandthoroughvalidationnecessitatesnotonlyawell-definedprocessbutalsoaproperenvironmentandtoolstofacilitateandexecutethemissionsuccessfully.IntelChandlerPlatformEngineeringgroupprovidespostsiliconsystemvalidation(SV)ofvariousmicro-controllersandprocessors.Thesystemvalidationprocesscanbebrokenintothreemajorparts.Thetypeofthedeviceanditsapplicationrequirementsdeterminewhichtypesoftestingareperformedonthedevice.TheAT89C51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afulldupleser-ialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsys-temtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscil-lator第5页disablingallotherchipfunctionsuntilthenexthardwarereset.VCCSupplyvoltage.GNDGround.Port0：Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.Port1：Port1isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/so-urcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Port2：Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoPort2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVXDPTR).Inthisapplication,itusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVXRI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsdurinFlashprogrammingandverification.第6页Port3：Port3isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sou-rcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepullups.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:RST：Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.ALE/PROG：AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduri-ngeachaccesstoexternalDataMemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.PSEN：ProgramStoreEnableisthereadstrobetoexternalprogrammemory.WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.EA/VPP：ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming,forpartsthatrequire12-voltVPP.XTAL1：Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.XTAL2：Outputfromtheinvertingoscillatoramplifier.Oscillator第7页CharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.IdleModeInidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.ToeliminatethepossibilityofanunexpectedwritetoaportpinwhenIdleisterminatedbyreset,theinstructionfollowingtheonethatinvokesIdleshouldnotbeonethatwritestoaportpinortoexternalmemory.Power-downModeInthepower-downmode,theoscillatorisstopped,andtheinstructionthatinvokespower-downisthelastinstructionexecuted.Theon-chipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepower-downmodeisterminated.Theonlyexitfrompower-downisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheon-chipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.TheAT89C51codememoryarrayisprogrammedbyte-bybyteineitherprogrammingmode.Toprogramanynonblankbyteintheon-chipFlashMemory,theentirememorymustbeerasedusingtheChipEraseMode.第8页2.ProgrammingAlgorithmBeforeprogrammingtheAT89C51,theaddress,dataandcontrolsignalsshouldbesetupaccordingtotheFlashprogrammingmodetableandFigure3andFigure4.ToprogramtheAT89C51,takethefollowingsteps.1.Inputthedesiredmemorylocationontheaddresslines.2.Inputtheappropriatedatabyteonthedatalines.3.Activatethecorrectcombinationofcontrolsignals.4.RaiseEA/VPPto12Vforthehigh-voltageprogrammingmode.5.PulseALE/PROGoncetoprogramabyteintheFlasharrayorthelockbits.Thebyte-writecycleisself-timedandtypicallytakesnomorethan1.5ms.Repeatsteps1through5,changingtheaddressanddatafortheentirearrayoruntiltheendoftheobjectfileisreached.DataPolling:TheAT89C51featuresDataPollingtoindicatetheendofawritecycle.Duringawritecycle,anattemptedreadofthelastbytewrittenwillresultinthecomplementofthewrittendatumonPO.7.Oncethewritecyclehasbeencompleted,truedataarevalidonalloutputs,andthenextcyclemaybegin.DataPollingmaybeginanytimeafterawritecyclehasbeeninitiated.2.1.Ready/Busy:TheprogressofbyteprogrammingcanalsobemonitoredbytheRDY/BSYoutputsignal.P3.4ispulledlowafterALEgoeshighduringprogrammingtoindicateBUSY.P3.4ispulledhighagainwhenprogrammingisdonetoindicateREADY.ProgramVerify:IflockbitsLB1andLB2havenotbeenprogrammed,theprogrammedcodedatacanbereadbackviatheaddressanddatalinesforverification.Thelockbitscannotbeverifieddirectly.Verificationofthelockbitsisachievedbyobservingthattheirfeaturesareenabled.Figure2-1-1ProgrammingtheFlashFigure2-2-2VerifyingtheFlash2.2.ChipErase:TheentireFlasharrayiserasedelectricallybyusingthepropercombinationofcontrolsignalsandbyholdingALE/PROGlowfor10ms.The第9页codearrayiswrittenwithall1s.Thechiperaseoperationmustbeexecutedbeforethecodememorycanbere-programmed.2.3.ReadingtheSignatureBytes:Thesignaturebytesarereadbythesameprocedureasanormalverificationoflocations030H,031H,and032H,exceptthatP3.6andP3.7mustbepulledtoalogiclow.Thevaluesreturnedareasfollows.(030H)=1EHindicatesmanufacturedbyAtmel(031H)=51Hindicates89C51(032H)=FFHindicates12Vprogramming(032H)=05Hindicates5Vprogramming2.4.ProgrammingInterfaceEverycodebyteintheFlasharraycanbewrittenandtheentirearraycanbeerasedbyusingtheappropriatecombinationofcontrolsignals.Thewriteoperationcycleisselftimedandonceinitiated,willautomaticallytimeitselftocompletion.Amicrocomputerinterfaceconvertsinformationbetweentwoforms.Outsidethemicrocomputertheinformationhandledbyanelectronicsystemexistsasaphysicalsignal,butwithintheprogram,itisrepresentednumerically.Thefunctionofanyinterfacecanbebrokendownintoanumberofoperationswhichmodifythedatainsomeway,sothatthe第10页processofconversionbetweentheexternalandinternalformsiscarriedoutinanumberofsteps.Ananalog-to-digitalconverter(ADC)isusedtoconvertacontinuouslyvariablesignaltoacorrespondingdigitalformwhichcantakeanyoneofafixednumberofpossiblebinaryvalues.Iftheoutputofthetransducerdoesnotvarycontinuously,noADCisnecessary.Inthiscasethesignalconditioningsectionmustconverttheincomingsignaltoaformwhichcanbeconnecteddirectlytothenextpartoftheinterface,theinput/outputsectionofthemicrocomputeritself.Outputinterfacestakeasimilarform,theobviousdifferencebeingthatheretheflowofinformationisintheoppositedirection;itispassedfromtheprogramtotheoutsideworld.Inthiscasetheprogrammaycallanoutputsubroutinewhichsupervisestheoperationoftheinterfaceandperformsthescalingnumberswhichmaybeneededfordigital-to-analogconverter(DAC).Thissubroutinepassesinformationinturntoanoutputdevicewhichproducesacorrespondingelectricalsignal,whichcouldbeconvertedintoanalogformusingaDAC.Finallythesignalisconditioned(usuallyamplified)toaformsuitableforoperatinganactuator.Thesignalsusedwithinmicrocomputercircuitsarealmostalwaystoosmalltobeconnecteddirectlytotheoutsideworldandsomekindofinterfacemustbeusedtotranslatethemtoamoreappropriateform.Thedesignofsectionofinterfacecircuitsisoneofthemostimportanttasksfacingtheengineerwishingtoapplymicrocomputers.Wehaveseenthatinmicrocomputersinformationisrepresentedasdiscretepatternsofbits;thisdigitalformismostusefulwhenthemicrocomputeristobeconnectedtoequipmentwhichcanonlybeswitchedonoroff,whereeachbitmightrepresentthestateofaswitchoractuator.Tosolvereal-worldproblems,amicrocontrollermusthavemorethanjustaCPU,aprogram,andadatamemory.Inaddition,itmustcontainhardwareallowingtheCPUtoaccessinformationfromtheoutsideworld.OncetheCPUgathersinformationandprocessesthedata,itmustalsobeabletoeffectchangeonsomeportionoftheoutsideworld.Thesehardwaredevices,calledperipherals,aretheCPUswindowtotheoutside.ThemostbasicformofperipheralavailableonmicrocontrollersisthegeneralpurposeI70port.EachoftheI/Opinscanbeusedaseitheraninput第11页oranoutput.Thefunctionofeachpinisdeterminedbysettingorclearingcorrespondingbitsinacorrespondingdatadirectionregisterduringtheinitializationstageofaprogram.EachoutputpinmaybedriventoeitheralogiconeoralogiczerobyusingCPUinstructionstopinmaybeviewed(orread.)bytheCPUusingprograminstructions.SometypeofserialunitisincludedonmicrocontrollerstoallowtheCPUtocommunicatebit-seriallywithexternaldevices.Usingabitserialformatinsteadofbit-parallelformatrequiresfewerI/Opinstoperformthecommunicationfunction,whichmakesitlessexpensive,butslower.Serialtransmissionsareperformedeithersynchronouslyorasynchronously.第12页中文翻译稿无线传感器网络3.AT89C51应用单片机广泛应用于商业：诸如调制解调器，电动机控制系统，空调控制系统，汽车发动机和其他一些领域。这些单片机的高速处理速度和增强型外围设备集合使得它们适合于这种高速事件应用场合。然而，这些关键应用领域也要求这些单片机高度可靠。健壮的测试环境和用于验证这些无论在元部件层次还是系统级别的单片机的合适的工具环境保证了高可靠性和低市场风险。Intel平台工程部门开发了一种面向对象的用于验证它的AT89C51汽车单片机多线性测试环境。这种环境的目标不仅是为AT89C51汽车单片机提供一种健壮测试环境，而且开发一种能够容易扩展并重复用来验证其他几种将来的单片机。开发的这种环境连接了AT89C51。本文讨论了这种测试环境的设计和原理，它的和各种硬件、软件环境部件的交互性，以及如何使用AT89C51。3.1.介绍8位AT89C51CHMOS工艺单片机被设计用于处理高速计算和快速输入/输出。MCS51单片机典型的应用是高速事件控制系统。商业应用包括调制解调器，电动机控制系统，打印机，影印机，空调控制系统，磁盘驱动器和医疗设备。汽车工业把MCS51单片机用于发动机控制系统，悬挂系统和反锁制动系统。AT89C51尤其很好适用于得益于它的处理速度和增强型片上外围功能集，诸如：汽车动力控制，车辆动态悬挂，反锁制动和稳定性控制应用。由于这些决定性应用，市场需要一种可靠的具有低干扰潜伏响应的费用-效能控制器，服务大量时间和事件驱动的在实时应用需要的集成外围的能力，具有在单一程序包中高出平均处理功率的中央处理器。拥有操作不可预测的设备的经济和法律风险是很高的。一旦进入市场，尤其任务决定性应用诸如自动驾驶仪或反锁制动系统，错误将是财力上所禁止的。重新设计的费用可以高达500K美元，如果产品族享有同样内核或外围设计缺陷的话，费用会更高。另外，部件的替代品领域是极其昂贵的，因为设备要用来把模块典型地焊接成一个总体的价值比各个部件高几倍。为了缓和这些问题，在最坏的环境和电压条件下对这些单片机进行无论在部件级别还是系统级别上的综合测试是必需的。IntelChandler平台工程组提供了各