文献翻译——一种新的非接触式智能IC卡，使用片上天线和一个异步微控制器

第1页外文文献资料WANewContact-lessSmartCardICUsinganOn-ChipAntennaandanAsynchronousMicro-controllerThispaperdescribesanewgenerationofContact-lessSmartCardChipwhichintegratesanon-chipcoilconnectedtoapowerreceptionsystemandanemitter/receivermodulecompatiblewiththeIS014443standard,togetherwithanasynchronousquasi-delayinsensitive(QDI)8-bitmicro-controller.BeyondtheContact-lessSmartCardapplicationfield,thisnewchipdemonstratesthatsystem-on-chipintegratingpowerreceptionandmanagement,radio-frequencycommunication,andsignalprocessingisfeasible.Itassociatesanalog/digitalpartsaswellassynchronous/asynchronouslogicsandhasbeenfabricatedinaCMOSsixmetallayers0.25-mtechnologyfromST-Micro-electronics.1.INTRODUCTIONTheSmartCardmarketentersanewera,withaboomingnumberofapplicationsinvariousdomainsandnewcountrieswillingtousethistechnology.SmartCardsarebecomingmoreandmoreubiquitousandthetrendistointegrateacardreaderinallkindofequipment(PCs,PDAs,mobilephones,etc.).E-commerce,citizenadministration,andotherscouldbe,throughtheInternet,goodvehiclestoallowserviceproviderstodevelopnewservicesusingtheSmartCardasahigh-securitykeyelement.Inthiscontext,contact-lessSmartCardsshouldplayanimportantpart.Theabsenceofcontactinduceslowermaintenancecost,improveseaseofuse,reliability,and,therefore,end-usersatisfaction.Theyaredeclinedinseveraltypesaccordingtothelocationoftheantenna.Itcanbeonthecard,onthemodule,orintegrateddirectlyonthechip.Thislatertechniquesignificantlydecreasescardfabricationcost.Moreover,astheuserstill第2页insertshiscardinareaderslot,transactionsremainassafeaswhenusingcardswithcontacts.Sincemostapplicationsrequirelow-costlow-powersystems,thegoalofthisworkistointegrateonasinglechipanantenna,anISO14443compliantradio-frequencyemitter/receiver,togetherwithanasynchronousmicro-controller.Integratingthewholesystemonsiliconshouldpavethewaytonewreliablelow-costContact-lessSmartCardchips.ThesemainkeytechnologiesusedtodesignthisnewSmartCardchiparepresentedinSectionII.TheSmartCardchipde-signisdetailedinSectionIII,andthedesignmethodologyisbrieflydescribedinSectionIV.ExperimentalresultsaregiveninSectionV.2.INNOVATIONTheinnovationofthischipliesintheassociationonthesamedieoftwokeytechnologies9:anintegratedpowerreceptionsystemwithanon-chipcoil5,andan8-bitCISCQDIasynchronousmicro-controller8.Thisassociationenablesustotakeadvantageoftheasynchronouslogicpropertiesinordertodecreasethedesignconstraintsoftheintegratedpowerreceptionsystemandalsotoincreasetheworkingdomainofthedigitalprocessingpart.Infact,theasynchronouslogichasthreeinterestingadvantagesvaluablefortheContact-lessSmartCardapplicationconsideredhere6,7.Insteadofbeingclockdriven,asynchronouscircuitsaredatadrivenwhichresultsinalowermean-powerconsumption.Insteadofimplementingacentralcontrolunit,asynchronouscircuitsimplementadistributedcontrolsystemwhichresultsinsmallercurrentpeaksandthenlowerelectromagneticemissionbecausetheelectricalactivityisspreadovertime.Finally,insteadofbeingclocktimed,asynchronouscircuitsareself-timedwhichenablesanautomaticregulationoftheperformance.Hence,QDIasynchronouscircuitsarenotsensitivetovoltagevariations,andrunsattheirmaximumspeedwithrespecttothepowerreceived.SincetheQDI8-bitmicro-controllerissorobustwithrespecttothepowersupplyvariations(seeSectionIII),thedesignofthepowerreceptionsystemismadeeasier:loweraveragepowerdelivered,aswellasthepeak第3页power,andsimplifiedregulationofthesupplyvoltage.Thisnotonlymakesthedesigneasier,butalsodecreasesthearea(smallerVDDsmoothingcapacitance).Finally,becauseofitslowcurrentpeakstheQDIasynchronousmicro-controllerdoesnotinterferewiththeloadmodulationusedintheISO14443standardforthecommunicationbetweenthecardandthereader.Thisenablesthemicro-controllertorunwhilethechipistransferringdatatothereaderwhichdecreasesthecomplexityofthesoftwareandthenthememoryspacerequirements.3.SMARTCARDCHIPDESIGNTheSmartCardchipiscomposedoffourmainblocks(Fig.1).TheRFfront-endrecoverspowerfromtheintegratedantenna,whichformsatransformerwiththeexternalreaderantenna.Therecoveredpoweristhenstabilizedandsuppliesthewholechip:theasynchronousmicro-controllerandasynchronousdedicatedinterfacebetweentheRFblockandtheasynchronouscircuit.Fig.1.Chiparchitecture.Thisinterfaceisdrivenbyareception-enablesignal(REN)controlledbythemicro-controller.Inreceptionmode,theRFinterfacedemodulatesdatasentbythereader.Inemissionmode,dataaresenttothereaderusingaloadmodulation.ThesystemisISO14443-Bcompliant10.WhentheSmartCardisinsertedinthereaderslot,assoonasthestabilizedsupplyreachesasufficientlevel,resetisactivatedbytheRFinterface.Themicro-controllerexecutesthebootprogramcontainedinROMandthenwaitsfordatacomingfromthereader.Thecommunicationbetweenthe第4页readerandtheSmartCardisfunctionallyasynchronous.ThecombinationoftheRENsignalandthestartandstopbits(thecommunicationbetweenthereaderandthechipismadeonanasynchronousmode,withstartandstopbits),encapsulatingthetransmittedbyteimplementsahalf-duplexcommunication.A.AnalogBlockDesignSincetherearenocontacts,poweranddataarerecoveredfromRFsignalsemittedbythereader.Theanalogblockisinchargeof1)poweringthechip;2)demodulating/modulatingdatafrom/tothereader;3)recoveringtheclockusedinthesynchronous/asynchronousinterface.Comparedtoothercontact-lesstechnologies7,thecardisinsertedinaslotwhichensuresthatthedistancechipreaderiskeptconstantandsmall:thevariationsindistancearewithinmillimeters.Thisenablestheintegrationofthecoilon-chip.Then,thereisnoneedforthevoltagewhichisrecoveredfromtheRFpowertobeverywellregulated,asitisthecaseforcontact-lesscardswhichoperateonatouchandgobasis.Thedesignofthepowermanagementandanalogblockcircuitryisaccordinglysimplified.TheblockdiagramoftheRFfront-endisdescribedinFig.2.Itisbuiltofthefollowingparts.1)Thefullwaverectifier(FWR)isabridgecomposedofnMOSandpMOStransistors.Theelectro-motive-force(EMF)inducedintheon-chipantennaisappliedtotheFWRinputs.Thenegativeoutputisconnectedtothebulkandthepositiveoutputisconnectedtoa500pFsmoothingcapacitor.ItdeliversthenonregulatedvoltageNRVtothechip.Fig.2.RFfront-endblockdiagram2)Theclockrecoveryblockextractsthe13.56-MHzclockfromtheRF第5页carriersignal.Forthispurpose,theinputofaSchmidttriggerisconnectedtooneofthetwoantennaterminals.3)Thepower-ondetector.Thisblockiscomposedofavoltagereference,adifferentialcomparatorandfilterstorejectmodulationparasitics.IttriggersaRESETwhentheNRVreachesagivenlevel.4)ThedatademodulatorisbasedonNRVamplitudetransitionsduetoNRZcodedtransmissionfromreadertochip.ThedatademodulatorextractsthedatamixedwithNRV,bydetectingnegativeandpositivetransitions.ThetwooutputsdrivetheinputsofanRSlatchwhichmakesthedataavailabletotheinterface.5)Theloadmodulatorisbuiltofaresistor(Rmod,seeFig.3)switchedbyannMOStransistorcontrolledbythedatatobesenttothereader.Itinducesanamplitudemodulationintheinductorantenna.Inemission,themodulatorhastomodulatethepowerabsorbedbythechipatan847-kHzBPSKrhythm.ThisismadebyamodulationofI(NRV),I2.ThisinducesanEMFinthereadersolenoid.Fig.3.Interfaceblockdiagram.B.Synchronous/AsynchronousInterfaceTheblockdiagramoftheinterfaceispresentedinFig.5.Itiscomposedofadivider,aBPSKmodulatorandablockwhichformatsthedatacomingfromtheexternalreaderandfromthemicro-controller.TheRF13.56-MHzcarrierisrecoveredanddividedtoprovidea847-kHzsignalusedtoclocktheinterface.OntheRFinterfaceside,bytesareencapsulatedwithstartandstopbitswhicharethenreceivedoremittedsequentiallyatthe847-kHzbitrate.Onthemicro-controllerside,anasynchronousfour-phasebundle-dataprotocolisused(8-bitdata,requestandacknowledge第6页signals)tocontroldataexchangewiththeQDIasynchronousmicro-controller.Thisinterfaceimplementstwotypesofconversion:protocolconversionandserial/parallelorparallel/serialconversions.Itisdesignedasasynchronousfinitestatemachineandtherefore,sometimingassumptionsaremadewhensamplingasynchronouscontrolsignalslikeP5reqandP4ack.Whenadatahastobeemittedfromthecard,theRENsignalisdisabledbythemicro-controllerwhichasksforwritingintotheinterfacebyassertingtheP5reqsignal.TheinterfaceanswersbyassertingP5ack.Thefour-phasehandshakeprotocolthencompleteswithtworeturn-to-zerophasesassoonastheonebytebufferisempty.Whenreceivingdatafromthereader,theRENsignalisdrivenhighandthemicro-controllerisreadytoreceiveaninputbytebyassertingtheP4acksignal.TheinterfaceanswersrisingtheP4reqsignalassoonasabyteisavailablefromthereceiver.Thehandshakethencompleteswiththereturn-to-zerophase.Thehandshakeprotocolensuresthatboththemicro-controllerandtheinterfaceareavailabletoacceptandtransmitabyteinemissionorreception.Thus,themicro-controllerwillbeidledaslongastheinterfacedoesnotgrantitsrequest.Theprogramexecutionwillresumewhenthedatabyteisfinallysentorreceived.Aone-bytebufferallowsthemicro-controllerandtheinterfacetorunconcurrently.Failuremayonlyoccurinreceptionifthemicro-controllerdoesnotreadtheincomingbyteintime.Inthatcase,theinterfaceoverwritethenon-readbyte.Thistypeofcommunicationfailurescanbesolvedusingsoftwareerror-checking.C.QDIAsynchronous8-bitMicro-controllerTheQDIasynchronous8-bitmicro-controllerisaCISCmachine,basedonadedicatedluxuriousmicro-architecture(Fig.6).InordertofacilitatethedesignofaCcompilerandalsotolimitmemoryaccesses,wedecidedtointegratetwodifferentregister-files:eight8-bitregistersaredevotedtodata,andeight16-bitregistersaredevotedtopointers(includingtheprogramcounterandthestackpointer).Specificarithmeticunitsareassociatedwitheachregisterfilesenablingconcurrentcomputationsofdataandaddresses.AdedicatedunitismanagingthestandardstatusbitsZ,N,V,第7页andC.Aperipheralunitisalsoincluded,supportingsix8-bitparallelports(oneinput,fouroutputs,and1bidirectionalusedtocontrolexternalflashmemoriesandthesynchronous/asynchronousinterface)andfourseriallinks(usingatwo-phasedelayinsensitiveprotocolcompatiblewithourhigh-performanceRISCasynchronousAsproprocessor4).Moreover,themicro-controllerintegrates16kBRAMand2kBROM.TheROMincludesaBuilt-In-Self-Test(BIST)programwhichisexecutedatresetaccordingtothebootmodeselected(eightmodesareavailable).Itisa350assemblyinstructionroutinewhichperformsastuck-at-faulttestwhichcomputesasignaturewritten,onthefly,ononeoftheparallelporttoreportonself-testprogress.TheQDIasynchronouslogicusedisself-testablebecauseastuck-atfaultonanyinputofanygatewillcauseahandshaketostopforever(noprematurefiring2).Asaresult,theBISTprogramwillneverproduceacompletesignature.Fig.6.Micro-controllerarchitecture.InstructionsetTheeight8-bitdataregistersarenamedr0tor7,andtheeight16-bitindexregistersi0toi7,wherei6andi7arethestack-pointerandtheprogram-counterrespectively.Thecontrollerimplementsthecommonarithmeticandlogicinstructions.Allinstructionsareencodedwithinoneword(16bits).Fourbasicaddressingmodesareavailable(immediate,register,indexed第8页withdisplacement,indexedpost-incrementedorpre-decremented)whichcanbeusedinconjunctionwithdataorindexregisteroperands.Lastly,thecontrollerimplementsamaskableinterruptmechanismandawaitforinterruptinstruction(Wfi).TableIsummarizestheinstructionset,notethecopy(Cp)andthePuch&Load(Pl)instructions.AcompletesoftwaredevelopmentsuiteoftoolsiscurrentlyunderdevelopmentincludingaCcompiler,anassembler,alinkerandasimulator.ArchitecturedesignThemicro-controllercoreisdesignedusingtheso-calledquasi-delayinsensitive(QDI)logic1,8.Afour-phaseprotocolisusedinconjunctionwithann-railencoding.Thismicro-controller,namedMICA,hasbeenavectorfordevelopingnewskillsinthedesignofstandard-cellbasedQDIasynchronouscircuits.ThedesignofMICAwasfocusedontwocorrelatedconcerns:designingdistributedasynchronousfinitestatemachineanddesigningforlowpower.Inordertoreducethepowerconsumptionofthemicro-controllerwehaveworkedonminimizingthenumberandtheenergycostofcommunicationactionsoccurringduringtheexecutionofeachinstruction,andminimizingthenumberofsequentialstepstoperformeachinstruction.Inotherwords,insteadofdesigningthearchitecturearoundalargecentralsequencer,wehavetriedtodistributethesequencingimplementationalloverthearchitectureasmuchaspossible.Theasynchronouslogicisparticularlywellsuitedtosatisfysuchadesignapproachsincebynaturethesequencingofanasynchronouscircuitisperformedbymultiplelocalsequencersimplementinghandshakingcommunicationsandlocaltreatments.4.DESIGNMETHODOLOGYTheSmartCardchiprepresentsacomplexsystemonchipwithseveraldifferentdesignstyles.Theanaloghasbeendesignedinfullcustom.Thesynchronous/asynchronousinterfacebetweentheanalog8blockandthemicro-controllerhasbeenmodeledusingVHDLasasynchronousfinitestatemachineandsynthesizedwithstandardCADtools.第9页Asregardstotheasynchronouslogic,themicro-controllerwasfirstdescribedinCHP1,ahigh-levellanguagewellsuitedtomodelasynchronouscircuits.Themodelwasthenrefinedtoobtainthefinaldistributedarchitecture.ModelvalidationwasperformedbyVHDLsimulation,thankstoaCHPtoVHDLtranslator3.ThesynthesisoftheCHPmodelintoQDIlogicwasperformedbyhandandtheschematicmanuallycapturedinastandarddesignframework.Themicro-controlleristhusbuiltof1)founderstandardcellsplussomespecificcells(Mullergates)andof2)foundersynchronouslow-powermemorieswithadditionalspecificinterfaces.Gate-levelandCHPco-simulationwasthenperformedinVHDLtovalidateeachblockaftersynthesis.Afterplace&route,thecompletesystem(excludedtheanalogblock)wasvalidatedbysimulatingaVHDLback-an-notatedgatelevelnetlist.Finally,aswitchlevelsimulationwasperformedtoestimatethecorepowerconsumptionandthusdeterminetheSmartCardpowerreceptionsystemcharacteristics.Fig.7describesthecompletedesignflowwehavesetup.5.EXPERIMENTALRESULTSThechipwasfabricatedattheSTMicroelectronicsCrollesplantusinga6metal-layer0.25-mCMOSprocess.Padsareincludedinthisfirstprototypeinordertotestthechipandperformmeasurementsonboththedigitalandanalogparts.Thetotalchipareais16mm2includingthesepads.Theon-chip-coilissurroundingthechip.Thecoilismadeofsixturnsimplementedwiththeupperfivemetallayers.Itsareais1.5mmTheCISCmicro-controllerwithitsmemoryrepresentsonemilliontransistors.Fig.4showsthestabilizationoftheNRVcurrentwithrespecttotheVDDcurrentvariation.Forvalidatingthechipinasystemenvironment,areaderconnectedtoaPCviaanRS232portwasdesigned.ThereaderincludestheRFoscillator,the10%ASKmodulator,theBPSKdetector,andprovides1Wunder6-Vconditions.Thechipwasintegratedonaprototypecard.Wheninsertingthecardintothereadermagneticfield(11gauss,withload),aprogramisdownloadedintothemicro-controllerRAManddataareexchangedbetweentheexternalPCandthe第10页card.Thecircuithasbeensuccessfullyvalidatedusingseveralprogramdownloading,likedumpingthemicro-controllerROMoridentifyingapinnumber.6.CONCLUSIONThechippresentedinthispaperisthefirstprototypethatfullyintegratesaContact-lessSmartCard(antenna,powerreception,RFcommunicationanddigitalprocessing).ItdemonstratesthatthedesignofsuchSystem-On-Chipisfeasibleusingthelatestindustrialtechnologies.Futureinvestigationswillfocusonthebenefitsoftheuseofanasynchronousmicro-controllerwithrespecttoareagain(VDDsmoothingcapacitor),designcomplexityreductionandsoftwaresimplification.AnotherveryinterestingandpromisingperspectiveistoinvestigatetheabilityofasynchronouscircuitstoimproveSmartCardcircuitsresistanceagainstwellknownattackssuchasDPAanalysis,faultandglitchattacks11.REFERENCES1A.J.Martin,SynthesisofasynchronousVLSIcircuits,Caltech,CS-TR-9328,1993.2H.Hulgaard,S.M.Burns,andG.Borriello,Testingasynchronouscircuits:Asurvey,Integration:theVLSIJournal,vol.19,pp.111131,1995.3M.Renaudin,P.Vivet,andF.Robin,Adesignframeworkforasynchronous/synchronouscircuitsbasedonCHPtoHDLtranslation,inProc.ASYNC,Barcelona,Spain,Apr.1999,pp.135144.4,ASPRO:an16-bitRISCasynchronousmicroprocessorwithDSPcapabilities,inESSCIRC,Duisburg,Germany,Sept.1999,pp.428431.5J.Bouvier,Y.Thorigne,S.A.Hassan,M.J.Revillet,andP.Senn,ASmartCardCMOScircuitwithmagneticpowerandcommunicationsinterface,inProc.ISSCC,SanFrancisco,CA,Feb.1997,pp.296297.6A.Abrial,J.Bouvier,M.Renaudin,andP.Vivet,Acontactless第11页Smart-Cardchipbasedonanasynchronous8-bitmicrocontroller,inAsynchronousCircuitsDesign(ACiD)Workshop,Grenoble,France,Jan./Feb.2000.7J.Kessels,T.Kramer,G.denBesten,andV.Timm,ApplyingasynchronouscircuitsinContactlessSmartCards,inProc.ASYNC,TelAviv,Israel,Apr.2000,pp.3644.8M.Renaudin,Asynchronouscircuitsandsystems:apromisingdesignalternative,MicroelectronicsforTelecommunications:ManagingHighComplexityandMobility,vol.54,no.1-2,pp.133149,Dec.2000.9Composantmicro-lectroniqueintgrantdesmoyensdetraitementnumriqueasynchroneetuneinterfacedecouplagelectromagntiquesanscontact,FrenchPatent9908485.10Identificationcardscontactlessintegratedcircuitscardsproximitycards,StandardISO/IECFCD144432.11D.P.Maher,Faultinductionattacks,tamperresistance,andhostilereverseengineeringinperspective,inProc.LNCS1318,FinancialCryptography,1997.第12页中文翻译稿一种新的非接触式智能IC卡，使用片上天线和一个异步微控制器本文介绍了新一代非接触式智能卡芯片，它集成了一个片上线圈，连接到一个电源接收系统和发射/接收模块符合ISO14443标准兼容，异步准延迟敏感（QDI）8位微控制器。这种新的芯片以外的非接触式智能卡的应用领域，演示了该系统的芯片集成功率接收和管理、射频通信和信号处理是可行的。它综合了模拟/数字以及同步/异步逻辑器件，并安装了一个意法半导体公司的0.25微米、CMOS六金属层的半导体。1.介绍智能卡市场进入了一个新时代,不断增长的应用于各种领域，新国家愿意使用这种技术。智能卡越来越无处不在,这一趋势是将读卡器整合在所有类型的设备(电脑、掌声电脑、手机等等)。公民管理，电子商务，以及其他可以通过互联网，良好的车辆，使服务提供商能够开发新的服务，使用智能卡的高安全性的关键因素。在这种背景下,非接触式智能卡扮演一个重要的角色。非接触诱导降低维护成本,提高了易用性、可靠性和终端用户的满意度。他们根据天线的位置减少了几种类型。它可以是上网卡,模块,或直接集成芯片上。后来的技术大大降低了卡的制造成本。此外，由于用户仍然将卡插在读卡器插槽，交易保持接触卡使用时的安全。由于大多数应用程序需要低成本的低功耗系统,这项工作的目标是在单个芯片上集成天线，符合ISO14443标准的射频发射器/接收器，异步微控制器。整个系统集成在硅片上，是一种新的可靠的低成本非接触式智能卡芯片的方式。设计这个新智能卡芯片的主要关键技术在第二部分给出。智能卡芯片设计的详细刊登在第三节,设计方法在第四节进行了简要评述。在第五部分给出了实验结果。2.创新该芯片的创新在于该协会位于同一芯片上的两个9的关键技术：一个带有片上线圈的集成接收系统5，和一个8位异步微控制器。这会使我们采取利用异步逻辑性能的方式，减少设计接收系统的集成功率的约束条件，并增加工作领域的数字处理部分。第13页事实上,异步逻辑对非接触式智能卡片的应用有三个有趣的优点6、7。而不是被时钟驱动，异步电路是数据驱动导致一个较低的平均功率消耗。而不是实现一个中央控制单元,异步电路实现分布式控制系统,形成较小的电流峰值,进而降低电磁辐射,由于电活动随时间分布。最后,而不是被时钟定时,异步电路计时自动调节性能。因此,异步电路QDI电压变化是不敏感的,并且在接收功率上运行最大的速度。由于QDI8位微控制器对电力供应的变化是有力的（见第三节），电力接收系统的设计变得更加容易：较低的平均功率交付,以及峰值功率,简化了供应电源的监管。这不仅使设计更简单,也减少了地区(更小的VDD平滑电容)。最后，因为它的低电流峰值QDI的异步单片机不会干扰负载调制，这种调制用于ISO14443标准之间的卡和读者的通信。这使得单片机运行而芯片是将数据传输到读者从而降低软件的复杂性和内存空间需求。3.智能CARDCHIP设计这种智能卡由四个主要模块组成（图1）。射频前端从集成天线恢复电力，这形成了一个具有外部天线的变压器。这种复原的电力是稳定的，供应整个芯片：异步单片机和一个连接射频模块与异步电路的同步专用接口。一个由微控制器控制的可接收信号驱动这个接口。在接收模式下，射频接口解调发送给读者的数据。在发射模式下，数据被发送给使用负载调制的读