外文翻译-单FPGA芯片实现的过流保护

英文原文OVERCURRENTRELAYONAFPGACHIPAbstractAnewhardwareapproachforimplementingovercurrentrelaysispresentedinthispaper.Anovercurrentrelayisimplementedonafieldprogrammablegatearray(FPGA)chip(XilinxsXC3020-50-PC84C).Thehardwaredesignoftheovercurrentrelayisbasedonathree-stagepipelinedarchitectureArelationshipthatdescribesthetime-currentcharacteristicsoftherelayintermsoftheclockfrequencyofthechipisdeveloped.1.INTRODUCTIONMicroprocessorshavesuccessfullyimplementedprotectivepowerrelays.Atypicalmicroprocessor-basedrelayrequiresmorethantengeneral-purposestandardchipsl23.Thebasicchipsnecessaryforimplementationincludeatleastread/writememory(RWM)chip,inputportinadditiontothemicroprocessor.Thedisadvantagesofusingseveralstandardchipsintheimplementationofaprotectiverelaycanbesummarizedinthefollowingpoints.1.Thesechipsconsumeboardspace.2.TheyrequirelabororProductiontimeforassembly.3.Theydecreasethereliabilitybecauseofthemechanicalconnections.4.Theyconsumepower.AdvancesinVeryLargeScaleIntegrated(VLSI)4systemshavemadethedesignandfabricationofApplication,SpecificIntegratedCircuits(ASICs)5feasible.ArecentlyintroducedtypeofASICisthefieldprogrammablegatearray（FPGA)6.FPGAsareASICswhichcombinetheattractivefeaturesofbothprogrammablelogicdevices(PLDs)7andgatearrays4.Thispaperreportsontheimplementationofanovercurrentrelayonafieldprogrammablegatearray(FPGA)chip,XilinxsXC3020-50-PC84C8.Xilinxsdevelopmentsystem8isusedforthesoftwareandhardwaredevelopmentoftheFPGAchip.Athree-stagepipelinedarchitectureisadoptedintherealizationoftherelayhardware.Theimplementedovercurrentrelayhastwos8-bitinputs:thecurrentbeingmonitoredandathresholdvalue;andtwosinglebitinputs:resetandclock.Theone-bittripsignalistheonlyoutputprovidedbytherelay.Thethresholdinput,whichcanbevaried,eterminestheminimumfaultcurrent.Theresetinputisprovidedforinitializationandresettingaftertripping.Ingeneral,aprotectiverelayonASICsuchasFPGAgivesthefollowingadvantges.a.Significantreductioninpowerconsumptionallboardspace.b.Nolabororproductiontimeforassembly.c.Nosoftwareprogramsarewrittenand/ordebugged.d.Productioncostisreducedwhileperfonnanceandreliabilityareincreased.Theoutlineofthispaperisasfollows.Section2describesthethree-stagedpipelinedarchitectureoftheovercurrentrelay.BriefdescriptionoftheFPGAchipandtheexperimentalresultsoftheovercurrentrelayarePresentedinsection3.Concludingremarksaregiveninsection42.ARCHITECTUREOFOVERCURRENTRELAYThebasicfunctionofanovercurrentrelayistomonitorthecurrentofthelinebeingprotected.Wheneverthecurrentexceedsapredeterminedthreshold,therelaygoesthroughadelayroutinethenactivatesthetripsignal.Figure1illustratesthetime-currentcharacteristicsoftheovercurrentrelay.Thebasicdigitalcircuitsneededfortheimplementationincludeacounter,look-uptableintheformofacombinationalcircuit,andtwocomparators.Thecountermeasuresthedurationofthefaultwhichmeansthatthevalueofthecounteriszeroundernormalconditions.Thelook-uptablestoresthetime-currentcharacteristics,showninFigure1,oftherelay.Thecomparatorsmaketwodecisions:Thefirstdecisioniswhetherthereisafaultornot;andtheseconddecisioniswhethertoactivatethetripsignalornot.Apipelinedarchitectureisselectedforthehardwarerealizationoftheovercurrentrelay.Pipelinedarchitecturesareregularandsimpletoimplementandatthesametimetheyprovidehighthroughput.OnlythreestagesareneededfortheovercurrentrelayasshowninFigure2.Inthefigurethestagesareseparatedbylatchesthatallowallthreestagestooperateinparallel.Theexecutiontimeofeachstageislessthanoneperiodofthesystemclock.Thereforethesystemclockpassesthedatathroughthesystembytriggeringthelatchessimultaneously.Thetasksofthethreestagesareoutlinedbelow.Stagel:Thefirststagehastwocircuits:thelook-uptableandacomparator.First,thetwoinputstothestage,thecurrentandthethresholdvalue,arelatched-in.Usingthecurrent,thetime-to-trip(ttt)isreadoutofthelook-uptable.Atthesametime,thecurrentandthethresholdvaluearecomparedandfaultcondition(fc)signaliscomputed.Thevalueoffcisequaltooneifandonlyifthecurrentexceedsthethresholdvalue,thatisFigure1Time-currentcharacteristicsofovercurrentrelaysOvercurrentrelayFigure2-PipelinedarchitectureforovercurrelltrelaysTheoutputstttamdfcofthefirststagearepassedtothesecondstage.Stage2:ThesecondstagehasonlyonecircuitthecounterItmeasuresthedurationofthefaultcurrentwheneverafaultoccurs.Ifthefaultconditionsignalfcisequaltoonethecounterisincremented,otherwisethecounterisclearedtozero.Therefore,thecountervalue(cv)isgivenby.(2)Thecountervalue(cv)alongwiththetime-to-tripsignalttt,whichisnotchanged，arepassedtothethirdstage.Stage3:Thesecondcomparatoristheonlycircuitinthethirdstage.ThecvandtttarecomparedandthetripsignalistheresultofthecomparisonThetripsignalbecomesoneifandonlyifcvisequaltoorgreaterthanttt,otherwiseitisequaltozero.Thetripsignalisalsotheoutputofthechipandhasspeciallatchingmechanism.Oncethetripsignalisactivated,thatisequaltoone,itwillonlygobacktozerothroughtheresetsignalofthechip.Theoveralloperationoftheovercurrentre1ayemergeswhenthetasksofthethreestagesarecombinedinthetimedomain.TheflowchartshowninFigure3providesacompleteviewoftherelayoperation.3.EXPERIMENTALRESULTSAfieldprogrammablegatearray(FPGA)chip,showninFigure4,isusedtoimplementtheovercurrentrelayarchitecturedescribedintheprevioussection.ThespecificchipemployedisXilinxsXC3020-50-PC84C8Ithasaninteriormatrixof64configurableconfigurablelogicblocksandasurroundingringof64configurableI/Ointerfaceblocks.Configurableinterconnectresourcesoccupythechannelsbetweentherowsandcolumnsofthelogicblocks,andbetweenthelogicblocksandtheI/Oblocks.Eachlogicblockhastwoflipflopsandinadditionitcanrealizeany5-inputlogicfunctionTheFPGAselectedisaprogramdrivenlogicdevice.Theconfigurablelogicblocks，I/Oblocks,andtheirinterconnectarecontrolledbyaconfigurationprogramstoredinanon-chipmemory.Theconfigurationprogramis1oadedautomaticallyfromanextemalPROMonpowcr-up.Xilinxsdevelopmentsystem8isusedtoenterthedesign,performthenecessarysimulation,andeventuallygeneratetheconfigurationprogram.Furthermore，thedevelopmentsystemisusedforin-circuitdesignverification.Figure3FlowchartfortheovecurrentrelayoperationThe0vercurtrelayrequires18inputpins:eightforthecurrent,eightforthethresholdvalues,onefortheclock,andoneforreset.Onlyoneoutputpinisneededforthetripsignal.Figure5showsasummaryoftheintemalblocksoftheFPGAthatareusedintheimplementationoftheovercurrentrelay.Inadditiontotheabovepins,9otherinputpillsareusedforthepower.AndcontrolpurposessuchasVcc,GND,andfordownloadingtheCedeintotheFPGA.Clearly,theactualdelayassociatedwitheachfaultcurrentdependsonthevaluettt,whichisstoredinthelook-uptable,aswellasthefrequencyoftheclockappliedtotheFPGAchip.Thisisduetothefactthatthetransferofinformationinthepipelinefromonestagetothenextiscontrolledbytheclock.Ourresultsshowthatforthefrequencies10MHz,60Hz,and1Hz,thefastestorinstanttripdelaysareequalto300nanosec,50msec,and3sec,respectively.Ingeneral,theactualtripdelayisgivenbythefollowingequation.13()TripDelaytf(4)OvercurrentrelayFigure5DesignsummaryWherefisthefrequencyoftheclockand3isthenumberofstagesinthepipeline,theexperimentalcharacteristicsoftheovercurrentrelaywhichreIatesthecurrenttotttisgiveninFigure6.Inotherwords,thelook-uptableshowninthefirststageofthepipelinedarchitectureinFigure2is,infact,ahardwarerealizationofthetablegiveninFigure6.Obviouslychangingthefrequencyoftheclockhasthesameeffectasmovingthetime-currentcharacteristics,showninFigurel,horizontally.HigherFrequenciesmovethecurvetotheleftwhilelowerfrequenciesmovethecurvetotheright.Ontheotherhand,themeasuringunitofthecurrentmaybecapableofmovingthetime-currentcurveverticallyThisisdonebychangingthescaleormultiplyingbyafactor.Therefore,changingtheclockfrequencyofthechipandthescaleofthecurrentmeasuringunitmayresultindifferenttime-currentcharacteristicsfortheovercurrentrelay.TheFPGAchipcaneasilybere-programmed.Ifthefrequencyoftheclockandthescaleofthemeasuringunitarekeptconstant,thetime-currentcharacteristicsoftheovercurrentrelaycanstillbechanged.Thisisachievedbychangingthecontentsofthelook-uptableinthedesignfileandthenre-programmingtheFPGAchip.4.CONCLUS10NAnovercurrentrelayhasbeenimplementedonaFPGAchip.Therelayhardwareconsistsoftwocomparators,acounter,andalook-uptable.Theimplementationisbasedonathree-stagepipelinedarchitecture.TheadvantagesofthepresenteddesignprocedureforimplementingovercurrentrelaysonFPGAsinclude:1.Onlyonechip,theFPGA,isneeded.ThereforealltheadvantagesofASICs,whicharementionedinSection1,arefeatured.2.FPGAsarenotexpensiveandtheirdevelopmentsystemsrunonPCs.3.TheselectedFPGAsareflexibleandcanbere-programmedtoaccommodateanychangesinthecharacteristicsoftheovercurrentrelay.4.Smallchangesinthecharacteristicsoftheovercurrentrelaycanbeaccomplishedbychangingthefrequencyoftheclockand/orchangingthescaleofthecurrentmeasuringunit.Figure6Characteristicsoftheimp中文译文单FPGA芯片实现的过流保护摘要本文介绍了一种新的过流继电器辅助执行装置。由Xinlinx的XC3020-50-PC84CFPGA芯片驱动过流继电器。过流继电器的硬件设计基于3级流水线结构。开发了按照时钟频率相关、描述继电器时间-电流特性的芯片。1介绍微处理器在电力继电保护上得到了成功的应用。一个典型的微机保护装置需要10个以上的一般意义的标准芯片。这类装置的基本组成至少包括微处理器、读写存储器、可编程只读存储器，输入/输出口。在一个继电保护装置中使用多个芯片的缺点可总结为以下几点：1这些芯片占用板子空间。2需要更多的劳动力或生产时间。3由于电气连接降低了可靠性。4费电。超大规模集成系统（VLSI）的发展已经使专用集成电路（ASIC）的设计和构造变得可行。最近的ASIC的类型是现场可编程门阵列（FPGA）。FPGA是融合了可编程逻辑器件和门阵列优点的专用集成电路。这篇论文介绍一种在FPGA上实现的过流保护装置。在继电保护硬件上采用三级流水线结构。过流保护装置有两个8位输入：监测电流和门值；两个一位的输入：复位和时钟。一位的三态信号是装置提供的唯一输出。不同门值的输入决定于最小故障电流。复位输入用于初始化和程序出错后的复位。一般来说，基于FPGA的继电保护装置有以下优点：a省电以及节省板内空间。b节省劳力或生产时间。c不需写或编译软件。d运行时费用降低，可靠性提高。本论文的目录如下：第二部分描述过电流保护的三级流水线结构；第三部分讲述FPGA芯片以及过流保护的实验结果；第四部分给出结论。2.过流保护的结构过流保护的基本作用是监视被保护线路的电流。一旦电流超过一个预定的值，继电器通过一个延时程序动作，并激活故障信号。图一说明了过流保护的时间与电流之间的关系。满足这种装置的基本数字电路包括一个计数器，反映组合电路结构的查找表，和两个比较器。计数器测量正常条件下计数器为零的故障的时间长度。查找表存储继电器时间与电流之间的关系特征，见图1。比较器做出两个决断。第一个判断是否故障；第二个决定是否发出故障信号。过流保护的硬件实现通过流水线结构来实现。流水线结构规整且容易实现，同时它有很大的吞吐量。过流保护只需三级，见图2。图中每一级通过锁存器分开，因此三级能并行运行。每一级的处理时间少于系统时钟的一个周期。因此系统时钟通过同时触发锁存器把数据送入系统。三级的任务如下：第一级：第一级有两个电路：查找表和一个比较器。首先，这一级的两个输入，电流和阈值被锁存。通过电流值，把时间和故障从查找表中读出。同时，比较电流和阈值，计算故障条件。有且仅有电流超过阈值，则故障条件的数值置为1。第一级ttt和fc的输出传送到第二级。锁存器电流阈值比较器1查找表计数器过电流比较器2tfcfctcv1级2级3级图2过电流继电器传输结构下级锁存器锁存器锁存器图1-时间-电流特性的过流继电器电流阈值时间(1)第二级：第二级只有一个计数器电路。一旦有故障它测量故障电流的持续时间。如果故障条件是1计数器计数，否则计数器清零。伴随着时间故障信号的计数器值不变，传送到第三级。(2)第三级：第三级只有一个比较器电路。Cv和ttt比较的结果就是故障信号的结果。如果cv大于ttt，故障信号置1，否则置零。故障信号也是芯片的输出，有着特定的锁存结构。一旦故障信号有效，芯片的复位信号会使它变为零。(3)当三级的任务在某一时段结合起来，过流保护的总体运行就发生了。图3中的图标显示的是保护运行的全貌。3实验结果图4通过使用在线可编程门阵列（FPGA）芯片来实现前面所讲的过流保护装置。芯片选用Xilinx的XC3020-50-PC84C。它有64个内部逻辑阵列块和64个可配置I/O口模块。