基于ATmega16的MP3设计与实现-外文翻译

外文原文TheAVRcorecombinesarichinstructionsetwith32generalpurposeworkingregisters.Allthe32registersaredirectlyconnectedtotheArithmeticLogicUnit(ALU),allowingtwoindependentregisterstobeaccessedinonesingleinstructionexecutedinoneclockcycle.TheresultingarchitectureismorecodeefficientwhileachievingthroughputsuptotentimesfasterthanconventionalCISCmicrocontrollers.TheATmega16providesthefollowingfeatures:16KbytesofIn-SystemProgrammableFlashProgrammemorywithRead-While-Writecapabilities,512bytesEEPROM,1KbyteSRAM,32generalpurposeI/Olines,32generalpurposeworkingregisters,aJTAGinterfaceforBoundary-scan,On-chipDebuggingsupportandprogramming,threeflexibleTimer/Counterswithcom-paremodes,InternalandExternalInterrupts,aserialprogrammableUSART,abyteorientedTwo-wireSerialInterface,an8-channel,10-bitADCwithoptionaldifferentialinputstagewithprogrammablegain(TQFPpackageonly),aprogrammableWatchdogTimerwithInternalOscil-lator,anSPIserialport,andsixsoftwareselectablepowersavingmodes.TheIdlemodestopstheCPUwhileallowingtheUSART,Two-wireinterface,A/DConverter,SRAM,Timer/Counters,SPIport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheregistercontentsbutfreezestheOscillator,disablingallotherchipfunctionsuntilthenextExternalInter-ruptorHardwareReset.InPower-savemode,theAsynchronousTimercontinuestorun,allowingtheusertomaintainatimerbasewhiletherestofthedeviceissleeping.TheADCNoiseReductionmodestopstheCPUandallI/OmodulesexceptAsynchronousTimerandADC,tominimizeswitchingnoiseduringADCconversions.InStandbymode,thecrystal/reso-natorOscillatorisrunningwhiletherestofthedeviceissleeping.Thisallowsveryfaststart-upcombinedwithlow-powerconsumption.InExtendedStandbymode,boththemainOscillatorandtheAsynchronousTimercontinuetorun.ThedeviceismanufacturedusingAtmelshighdensitynonvolatilememorytechnology.TheOn-chipISPFlashallowstheprogrammemorytobereprogrammedin-systemthroughanSPIserialinterface,byaconventionalnonvolatilememoryprogrammer,orbyanOn-chipBootprogramrunningontheAVRcore.ThebootprogramcanuseanyinterfacetodownloadtheapplicationprogramintheApplicationFlashmemory.SoftwareintheBootFlashsectionwillcontinuetorunwhiletheApplicationFlashsectionisupdated,providingtrueRead-While-Writeoperation.Bycombiningan8-bitRISCCPUwithIn-SystemSelf-ProgrammableFlashonamonolithicchip,theAtmelATmega16isapowerfulmicrocontrollerthatprovidesahighly-flexibleandcost-effec-tivesolutiontomanyembeddedcontrolapplications.TheATmega16AVRissupportedwithafullsuiteofprogramandsystemdevelopmenttoolsincluding:Ccompilers,macroassemblers,programdebugger/simulators,in-circuitemulators,andevaluationkits.TheinterconnectionbetweenMasterandSlaveCPUswithSPIisshowninFigure66.ThesystemconsistsoftwoShiftRegisters,andaMasterclockgenerator.TheSPIMasterinitiatesthecommunicationcyclewhenpullinglowtheSlaveSelectSSpinofthedesiredSlave.MasterandSlavepreparethedatatobesentintheirrespectiveShiftRegisters,andtheMastergeneratestherequiredclockpulsesontheSCKlinetointerchangedata.DataisalwaysshiftedfromMastertoSlaveontheMasterOutSlaveIn,MOSI,line,andfromSlavetoMasterontheMasterInSlaveOut,MISO,line.Aftereachdatapacket,theMasterwillsynchronizetheSlavebypullinghightheSlaveSelect,SS,line.WhenconfiguredasaMaster,theSPIinterfacehasnoautomaticcontroloftheSSline.Thismustbehandledbyusersoftwarebeforecommunicationcanstart.Whenthisisdone,writingabytetotheSPIDataRegisterstartstheSPIclockgenerator,andthehardwareshiftstheeightbitsintotheSlave.Aftershiftingonebyte,theSPIclockgeneratorstops,settingtheendofTransmissionFlag(SPIF).IftheSPIInterruptEnablebit(SPIE)intheSPCRRegisterisset,aninterruptisrequested.TheMastermaycontinuetoshiftthenextbytebywritingitintoSPDR,orsignaltheendofpacketbypullinghightheSlaveSelect,SSline.ThelastincomingbytewillbekeptintheBufferRegisterforlateruse.WhenconfiguredasaSlave,theSPIinterfacewillremainsleepingwithMISOtri-statedaslongastheSSpinisdrivenhigh.Inthisstate,softwaremayupdatethecontentsoftheSPIDataRegister,SPDR,butthedatawillnotbeshiftedoutbyincomingclockpulsesontheSCKpinuntiltheSSpinisdrivenlow.Asonebytehasbeencompletelyshifted,theendofTransmissionFlag,SPIFisset.IftheSPIInterruptEnablebit,SPIE,intheSPCRRegisterisset,aninterruptisrequested.TheSlavemaycontinuetoplacenewdatatobesentintoSPDRbeforereadingtheincomingdata.ThelastincomingbytewillbekeptintheBufferRegisterforlateruse.VS1003isasingle-chipMP3/WMA/MIDIaudiodecoderandADPCMencoder.Itcontainsahighperformance,proprietarylow-powerDSPprocessorcoreVSDSP4,workingdatamemory,5KiBinstructionRAMand0.5KiBdataRAMforuserapplications,serialcontrolandinputdatainterfaces,4generalpurposeI/Opins,anUART,aswellasahigh-qualityvariable-sample-ratemonoADCandstereoDAC,followedbyanearphoneamplifierandagroundbuffer.VS1003receivesitsinputbitstreamthroughaserialinputbus,whichitlistenstoasasystemslave.Theinputstreamisdecodedandpassedthroughadigitalvolumecontroltoan18-bitoversampling,multi-bit,sigma-deltaDAC.Thedecodingiscontrolledviaaserialcontrolbus.Inadditiontothebasicdecoding,itispossibletoaddapplicationspecificfeatures,likeDSPeffects,totheuserRAMmemory.(1)SPIBusesTheSPIBus-thatwasoriginallyusedinsomeMotoroladevices-hasbeenusedforbothVS1003sSerialDataInterfaceSDI(Chapters7.4and8.4)andSerialControlInterfaceSCI.(2)DataRequestPinDREQTheDREQpin/signalisusedtosignalifVS1003sFIFOiscapableofreceivingdata.IfDREQishigh,VS1003cantakeatleast32bytesofSDIdataoroneSCIcommand.Whenthesecriteriaarenotmet,DREQisturnedlow,andthesendershouldstoptransferringnewdata.Becauseofthe32-bytesafetyarea,thesendermaysendupto32bytesofSDIdataatatimewithoutcheckingthestatusofDREQ,makingcontrollingVS1003easierforlow-speedmicrocontrollers.Note:DREQmayturnloworhighatanytime,evenduringabytetransmission.Thus,DREQshouldonlybeusedtodecidewhethertosendmorebytes.Itshouldnotabortatransmissionthathasalreadystarted.Note:InVS10XXproductsuptoVS1002,DREQwasonlyusedforSDI.InVS1003DREQisalsousedtotellthestatusofSCI.(3)SerialProtocolforSerialDataInterface(SDI)TheserialdatainterfaceoperatesinslavemodesoDCLKsignalmustbegeneratedbyanexternalcircuit.Data(SDATAsignal)canbeclockedinateithertherisingorfallingedgeofDCLK.VS1003assumesitsdatainputtobebyte-sychronized.SDIbytesmaybetransmittedeitherMSborLSbfirst,dependingofcontentsofSCIMODE.ThefirmwareisabletoacceptthemaximumbitratetheSDIsupports.InVS1002nativemodes(SMNEWMODEis1),bytesynchronizationisachievedbyXDCS.ThestateofXDCSmaynotchangewhileadatabytetransferisinprogress.ToalwaysmaintaindatasynchronizationeveniftheremaybeglitchesintheboardsusingVS1003,itisrecommendedtoturnXDCSeverynowandthen,forinstanceonceaftereveryflashdatablockorafewkilobytes,justtokeepsurethehostandVS1003areinsync.IfSMSDISHAREis1,theXDCSsignalisinternallygeneratedbyinvertingtheXCSinput.Fornewdesigns,usingVS1002nativemodesarerecommended.(4)SerialProtocolforSerialCommandInterface(SCI)TheserialbusprotocolfortheSerialCommandInterfaceSCI(Chapter8.5)consistsofaninstructionbyte,addressbyteandone16-bitdataword.Eachreadorwriteoperationcanreadorwriteasingleregister.Databitsarereadattherisingedge,sotheusershouldupdatedataatthefallingedge.BytesarealwayssendMSbfirst.Theoperationisspecifiedbyan8-bitinstructionopcode.Thesupportedinstructionsarereadandwrite.Note:VS1003setsDREQlowaftereachSCIoperation.Thedurationdependsontheoperation.ItisnotallowedtostartanewSCI/SDIoperationbeforeDREQishighagain.MP3audioqualityForMP3isalossycompressionformat,itoffersavarietyofdifferentbitrate(bitrate)option-thatisusedtorepresentasecondaudioencodingdataneededforthefigures.Typicalspeedbetween128KBPSand320KBPS(kbit/s).Incontrast,theCDonuncompressedaudiobitrateis1411.2KBPS(16/samplepointx44100x2channelsamplingHP/SEC).UsinglowbitratecodingMP3fileplaybackqualityisusuallylow.Usinglowbitrate,thecompressnoise(compressionwillanartifact)(no)intheoriginalrecordingwillbepresentedduringplayback.Agoodexampleofcompressnoiseis:theshoutofcompression;Becauseofitsrandomnessandrapidchange,sotheencodererrorswillbemoreobvious,anditsoundslikeecho.Inadditiontothecodefilebitrate;ThequalityoftheMP3file,alsorelatedtothequalityoftheencoderandthedifficultyofthecodedsignal.Usinghighqualitygeneralsignalencoderencoding,somepeoplethinkthat128kbit/s(MP3and44.1kHzCDsamplingsoundsimilartoCDquality,atthesametimegetaboutnowthecompressionratio.UndertheratioofcorrectcodingofMP3canonlygetbettersoundqualitythanFMradio,thisbasicallyisthesimulationofthemediumbandwidthconstraints,signal-to-noiseratioandotherrestrictions.Hearingtests,however,showthesimpleexercisetestaudiencecanreliablydistinguishthedifferencebetweenthe128kbit/s(MP3andoriginalCD.InmanycasestheythinkMP3soundqualityistoolow,isnotacceptable,butsomeotheraudienceorchangetheenvironment,suchasinanoisycar)orthepartytheythinkthequalityisacceptable.Obviously,thedrawbacksofMP3encodingonlow-endsoundCARDSorspeakersarelessobviousandhighqualitystereointheconnectiontothecomputersystem,especiallywhenusingthehi-fiequipmentorhighqualityheadphonesismoreobvious.中文翻译AVR内核具有丰富的指令集和32个通用工作寄存器。所有的寄存器都直接与算逻单元(ALU)相连接，使得一条指令可以在一个时钟周期内同时访问两个独立的寄存器。这种结构大大提高了代码效率，并且具有比普通的CISC微控制器最高至10倍的数据吞吐率。ATmega16有如下特点:16K字节的系统内可编程Flash(具有同时读写的能力，即RWW)，512字节EEPROM，1K字节SRAM，32个通用I/O口线，32个通用工作寄存器，用于边界扫描的JTAG接口，支持片内调试与编程，三个具有比较模式的灵活的定时器/计数器(T/C),片内/外中断，可编程串行USART，有起始条件检测器的通用串行接口，8路10位具有可选差分输入级可编程增益(TQFP封装)的ADC，具有片内振荡器的可编程看门狗定时器，一个SPI串行端口，以及六个可以通过软件进行选择的省电模式。工作于空闲模式时CPU停止工作，而USART、两线接口、A/D转换器、SRAM、T/C、SPI端口以及中断系统继续工作；掉电模式时晶体振荡器停止振荡，所有功能除了中断和硬件复位之外都停止工作；在省电模式下，异步定时器继续运行，允许用户保持一个时间基准，而其余功能模块处于休眠状态；ADC噪声抑制模式时终止CPU和除了异步定时器与ADC以外所有I/O模块的工作，以降低ADC转换时的开关噪声；Standby模式下只有晶体或谐振振荡器运行，其余功能模块处于休眠状态，使得器件只消耗极少的电流，同时具有快速启动能力；扩展Standby模式下则允许振荡器和异步定时器继续工作。本芯片是以Atmel高密度非易失性存储器技术生产的。片内ISPFlash允许程序存储器通过ISP串行接口，或者通用编程器进行编程，也可以通过运行于AVR内核之中的引导程序进行编程。引导程序可以使用任意接口将应用程序下载到应用Flash存储区(ApplicationFlashMemory)。在更新应用Flash存储区时引导Flash区(BootFlashMemory)的程序继续运行，实现了RWW操作。通过将8位RISCCPU与系统内可编程的Flash集成在一个芯片内，ATmega16成为一个功能强大的单片机，为许多嵌入式控制应用提供了灵活而低成本的解决方案。ATmega16具有一整套的编程与系统开发工具，包括：C语言编译器、宏汇编、程序调试器/软件仿真器、仿真器及评估板。主机和从机之间的SPI连接如Figure66所示。系统包括两个移位寄存器和一个主机时钟发生器。通过将需要的从机的SS引脚拉低，主机启动一次通讯过程。主机和从机将需要发送的数据放入相应的移位寄存器。主机在SCK引脚上产生时钟脉冲以交换数据。主机的数据从主机的MOSI移出，从从机的MOSI移入；从机的数据从从机的MISO移出，从主机的MISO移入。主机通过将从机的SS拉高实现与从机的同步。配置为SPI主机时，SPI接口不自动控制SS引脚，必须由用户软件来处理。对SPI数据寄存器写入数据即启动SPI时钟，将8比特的数据移入从机。传输结束后SPI时钟停止，传输结束标志SPIF置位。如果此时SPCR寄存器的SPI中断使能位SPIE置位，中断就会发生。主机可以继续往SPDR写入数据以移位到从机中去，或者是将从机的SS拉高以说明数据包发送完成。最后进来的数据将一直保存于缓冲寄存器里。配置为从机时，只要SS为高，SPI接口将一直保持睡眠状态，并保持MISO为三态。在这个状态下软件可以更新SPI数据寄存器SPDR的内容。即使此时SCK引脚有输入时钟，SPDR的数据也不会移出，直至SS被拉低。一个字节完全移出之后，传输结束标志SPIF置位。如果此时SPCR寄存器的SPI中断使能位SPIE置位，就会产生中断请求。在读取移入的数据之前从机可以继续往SPDR写入数据。最后进来的数据将一直保存于缓冲寄存器里。VS1003是一个单片MP3/WMA/MIDI音频解码器和ADPCM编码器。它包含一个高性能，自主产权的低功耗DSP处理器核VS_DSP4,工作数据存储器，为用户应用提供5KB的指令RAM和0.5KB的数据RAM。串行的控制和数据接口，4个常规用途的I/O口，一个UART，也有一个高品质可变采样率的ADC和立体声DAC，还有一个耳机放大器和地线缓冲器。VS1003通过一个串行接口来接收输入的比特流，它可以作为一个系统的从机。输入的比特流被解码，然后通过一个数字音量控制器到达一个18位过采样多位-DAC。通过串行总线控制解码器。除了基本的解码，在用户RAM中它还可以做其他特殊应用，例如DSP音效处理。(1)SPI总线SPI总线，最初被用在一些Motorola器件上-也被应用于VS1003的串行数据接口SDI和串行控制接口SCI。(2)数据请求脚DREQDREQ脚，在VS1003的FIFO在能够接受数据的时候输出高电平。此时，VS1003可获取至少32Byte的SDI数据或一个SCI命令。遵循这个标准，当DREQ变低时，发送器必须停止发送新的数据。因为有32Byte的保险区域（数据缓冲区）,当检测到DREQ信号时，发送器（MCU）须发送32Byte的SDI数据。易于和