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第1页外文文献资料DigitalWaveformGeneratorBasedonFPGAAbstract:FieldProgrammableGateArray(FPGA)oftheCycloneIIserieswasasthecoreprocessoroffrequencymeterandtheIIwasastheQuartsdevelopmentplatform.Thisarticlehaddesignedthefullydigitalsignalgenerator.Itusedall-digitalfrequencysynthesizertechnologyandFPGAprogrammingimplementedthethreewaveforms:sinwaveandsquarewaveandtrianglewave.Thefrequencywasadjustablethrough10-bitphaseaccumulatorandtheanalogmultiplierachievedamplitudemodulation.Using51softnuclearFPGAwroteaCprogramandrealizedtheinputcontrolword.The44matrixkeyboardinputtedfrequencyoramplitudevalueandtheLCD1602displayedthem.Thetestresultsshowthatthesystemhashighprecision,distortionandlow.1.IntroductionWaveformgeneratorisanindispensabletoolforallkindsoftestandexperimentanditisalsohaveveryextensiveapplicationforcommunication,measuring,radar,controlandteachingfield.Bothinproduction,scientificresearchorintheteaching,waveformgeneratorarethebesttoolsforelectronicengineerstodothesimulationexperimentofsignal.Alongwiththedevelopmentofourcountryeconomyandscienceandtechnology,thecorrespondingtestequipmentandtestingmethodputforwardhigherrequestandwaveformgeneratortestinstrumenthasbecomeveryimportant,soithasimportantsignificancetodevelopwaveformgenerator(Zhangetal.,2011;LiandMa,2010;Fengetal.,2010;Luo,2011).TheFPGAisprogrammableICandithasthehighestintegrationandcomplexity(Zhangetal.,2011).TheFPGAcanimplementthearithmeticlogicunit,themultiplier,thedigitalfiltersandthetwo-dimensionalconvolution,第2页etc.,withthelogicaldesignofthelogicalunitofcomplexalgorithmsandsignalprocessingunitanditcanrepeatprogrammingforinfinitetimesanditalsocanmodifyanduninstallthefinisheddesigninthesamedeviceandalotofnumberofbasiccomponentsontheFPGA,whichmakesaverycomplexelectroniccircuitdesignintosomethingmorethanreality(Baoetal.,2008).Inrecentyears,theFPGAtechnologyobtainedarapiddevelopmentandextensiveapplicationofgreatlyincreaseofitsresourcecapacity,workingfrequencyandintegrationandtheuseofFPGAgotattentioninrealizingsomespecialdigitalintegratedcircuitanddirectdigitalfrequencysynthesizerbasedonFPGAhasthemoreadvantages(LiandMa,2010).Theadvantagesarethatithasaflexibleinterfaceandthecontrolmode,arelativelyshortperiodoftime,awideconversionbandwidthandphasechangeandcontinuousfrequencyresolutionishigher.ItalsoprovidesanothermethodfordesignersbasedonintegratedrealizationcircuitistheFPGAtechnologyintherealizationoftheapplicationforDDSsystemofdigitalpartdesign.FirstwewillmeettheproblemoftransmissionacrosstheclockthatisverytypicalintheFPGAdesign.Theoutputofthesinglechipmicrocomputerclockis:smagnitudeandFPGAdigitalsystemisthensmagnitude,sothetransmissionspeedmatchingdirectlyaffectsthestabilityoftheinputcontrolword.ThisstudytookFPGAassignalgenerator.FrequencyoramplitudevalueisinputfromthekeyboardanditwillbedisplayedintheLCD1602.FrequencyoramplitudevalueisconvertedtofrequencyoramplitudecontrolwordsenttotheDDSthroughthemicrocontroller.Moreover,thedirectnumericalfrequencysynthesizerbasedonFPGAhasalotofbenefits,suchasflexiblejoggleandwaytocontrol,relativelyshorttransmutingtime,relativelybroadbelt,thesuccessionofchangeofphasepositionandhighscreenresolution,etc.2.DDSTECHNOLOGYTheDirectDigitalfrequencySynthesistechnology(DDS)isanewtechnologyoffrequencysynthesisandwaytoproducesignal(Fengetal.,2010).ThetraditionaldigitalmethodofproducingsinewaveistomakeuseofapieceofROM,apieceofDACandtheaddresscounter.Inordertomake第3页outputfrequencymoreconvenient,itcanusephasepositionaccumulator,whichmakesoutputfrequencyproportionaltotheproductofclockfrequencyandtheincrementofphaseposition.ItisshowninFig.1.Thedirectsyntheticsystemwhichappliesthemethodofphasepositionaccumulatormakestheaccuracyofthesinewaveonthephaseistakenasthen-bit,thentheresolutionratioamountsto.Itfetcheseachpointonthenumerical1/2nphasepositioncircle(thenumberusedasaddress)andreadsthesinewaveamplitudevalueofROMandreconstitutesthesinewavethroughDAC.Thefunctionofphasepositioninthissystemistofetchanumbereveryotherkpointswhenreadingeachpointonthenumericalphasepositioncircle(kisthefrequencycontrolword).Inthisway,theDACoutputsinewavefrequencyisformula(1):(1)sin(/2nclkffIntheformula,isaclockofDDS;nisusuallyinbetween24and32.clkfTheDDScoreisphasepositionaccumulator.Itislikeacommoncalculator,butitiscomposedofn-bitadderandn-bitphasepositionregister.Whenaclockpulsecomes,theoutputofthephaseregisterwilladdasstepphaseincrementvalue.Theadderaddsthefrequencycontrollingdataandtheaccumulatingphasepositiondataoutputtedbyaccumulatingregisterandsendstheresulttothedatainputterminaloftheaccumulatingregister.Thephasepositionaccumulatorcomesintolinearityphasepositionaccumulation,totheextentofproducingacountingoverflow,whosefrequencyistheoutputfrequencyofDDS.ThesinepollinglistisaprogrammablePROM.Itstoresaperiodicsine-signalsamplingvalueofencodingwithregardingaphasepositionasitsaddress.Itcontainsinformationofnumericalrangeofperiodicsinewaveandeachaddresscorrespondstoaphasepointoftherangefrom0-360degreeinsinewave.Ifweaddtheoutputofphaseregistertophasecontrollingdata,wecangetadatawhichcanbeusedasanaddresstoaddressingsinepollinglist.Thelistmapstheinputtedaddressinformationintosinewaverangesignal,drivesDACandoutputstheanalogsignal(Liuetal.,2009a).第4页Km-bits-bitFclkFoutno-bitphaseaccumulatorLookuptableROMDACFig.1:DDScomposite2.1.DDSparametersForthecountcapacityphaseaccumulatorandsinewavewaveformmemory2nofasamplingpointphaseofm,ifthefrequencycontrolcharacterisk,theoutputsignalfrequencyforandthereferenceclockfrequencyfor,sinfclkfthenthesystemoutputsignalfrequencyisformula(2):(2)sin/nclkfThefrequencyresolutionoftheoutputsignalfrequencyisformula(3):(3)min/nclkfFromtheNyquistsamplingtheorem,itisknownthatthelargestfrequencyoftheDDSoutputisformula(4):(4)max/2clkfThekoffrequencycontrolwordcanbelaunchedbytheaboveformulaanditisformula(5):(5)sin*2/clkkffwhenthefrequencyofexternalreferenceclockis50MHzandtheoutputfrequencyis1MHz,aftersixtimesfrequencyofthesystemclock,thenmakeinto300MHz,itcanusetheaboveformulacalculatedcontrolfrequencyclkfwordthattheDDSneedtoset:k=248/300.2.1.DDScomposition:DDS.vhdtopdesignprincipleisshowninFig.2.ItiscompiledintheQuartusIIenvironment.TheisFPGA/CPLDdevelopmentintegrationQuarts第5页environmentthatprovidedbythecompanyanditprovidesadesignAlteraenvironmentthathasnothingtodowiththestructure,sodesignerscandesigninputeasily,processrapidlyanddeviceprogramming.designQurtstoolsfullysupportthedesignprocessofVHDLandanditsinternallogVeristuddedwithVHDL,logicsynthesisdevice.Also,havelogVeriatsimulationfunction,butalsosupportthethirdpartysimulationtools.includemodularcompiler.ThemodulecompilerincludesthefunctionQuartsofanalysis/comprehensivedevice,adapter,withinstruments,timinganalyzer,compiledatainterface,etc(MaandWang,2011).Fig.2:DDS.vhdtopprinciplediagram3.K8051SOFT-COREMICROCONTROLLERANDKEILSOFTWAREThechipmicrocomputer89C51isalowvoltageandCMOS8-bitmicroprocessorwith4kbitsFlashprogrammableanderasablereadonlymemory.89C2051isachipmicrocomputerofFPEROM-FlashProgrammableanderasablereadonlymemorywith2kbits.Thechipmicrocomputeroferasablereadonlymemorycanbeerased100times.ItsdeviceappliesATMELandiscompatiblewithindustrialstandardMCS-51.Becauseofmultifunctional-figureCPUandflashmemorycomposedinasingleslug,89C51ofATMELisanefficientmicrocontrollerand89C2051isitssimplifiedversion(Liuetal.,2009b).LinktheROMandRAMto8051softnuclear,itbecomesthecomplete8051singlechipmicrocomputer.TheMCS51microcontrollerCPUalsobelongstoCISCCPU.K8051microcontrollerisVQMbytheoriginalcode(logVeriQuartsMappingFile)toexpress,inIIenvironmentitcanbewithVHDL,QuartsandotherhardwaredescriptionlanguagemixedcompilecomprehensivelogVeriandinasinglepieceofFPGA,itcanrealizeallhardwaresystemand第6页completethesoftwaredebugging.K8051microcontrollernuclearalsocontains8-bircomplexinstructionsanditsmemoryusesHarvardstructure.K8051instructionsystemand8051/2and8031/2arefullycompatibleandhardwareisalsobasicsame.Forexample,itmaymeet64KBexternalstorageandalsomaymeet256bytesinternaldataRAManditincludestwo16timing/counter,full-duplexserialportsthepowerconsumptionofthesaveworkmodeandinterruptresponsestructureandsoon.Keilisthe51SCMdevelopmentsoftwareplatforms.TheKeil:Vision2canbesimulationsoftware.Toconnect51SCMintothehardwareemulatorandloadtheprojectprogramintheemulator,thenitcanachieverealtimesimulation.Itcanalsouse:Vision2embeddedmodule,theKeilmonitor-51,undernoadditionalhardwareemulatorconditions,connectedtothemicrocontrollerhardwaresystemandachievereal-timesimulationfortheprojectprogram.Whenthesystemstartswork,firstinitializethesystemandthenexecutekeyboardscansubroutine,buttonsforidentification.Indataprocessingprocedure,thesystemwillbethekeyboardinputkeysofmanytimesforthecorrespondingfrequencyconversionoramplitudevalueandtheP1tomouth.ThisfrequencyoramplitudevalueusingtheformulamethodistransformedintothefrequencyoramplitudecontrolwordsenttotheP0portthatisconnectedtotheDDS,sothecontrolwordissenttotheDDS.CallLCDdisplayroutinesandthefrequencyormagnitudevalueoftheP1portisdisplayedintheLCDmonitor.Afterthewholeprogramexecution,theprogramreturnstothekeyboardscanningsubroutine,successiveowntoexecution.ReferencefrequencysourceWaveROMDACLow-passfilterno-bitphaseaccumulatorFig.3:DDSprincipaldiagram第7页4.KEYTECHNOLOGIESSignalmodule:Withrandomread/writememoryforstorageofthewaveformRAMquantitativedata,accordingtothedifferentfrequency,attherequestofthefrequency,controlwordKisassteppingonphaseincrementalcohorts,toaccumulatephasevalueforexistingandreadwaveformdatawithinthememoryaddress.D/Aconverterandamplitudecontrolandthenfilteredtogetthedesiredwaveform.BecauseDDShastherelativebandwidthwidely,thefrequencyconversiontimeisshortly(butlessthan20microsec)andthefrequencyresolutionisalsohigher(Fengetal.,2010).All-digitalarchitecturefacilitatestheintegrationandoutputphase-continuous,frequency,phaseandamplitudecanbeprogrammedtoachieve.TheDDSprinciplediagramisshowninFig.3.DDStechnologyhashighresolution,frequencyconversionspeed,highpurity,phasesignalcontrollable,outputsignalnocurrentpulseoutputcanstack,smoothtransitionandphasecankeepcontinuouschange.Displaymodule:TheLCDcandisplayallcharactersandcustomcharactersandcanalsoshowsthatmanysetsofdataofChinesecharactersandthecharactersisclear.Becauseofitsowncontroller,notonlycanreducetheburdenofthesinglechipmicrocomputer,butalsocanachievetheresultthatdrivemodeofmenuandrealizethefullscreenedittheeditormodulefunction,tofriendlyhuman-machineinterface.LCDdisplaycansolveLEDdisplaynumbersonlyseveralsimplecharactershortcomings(DingandLi,2011).Ithastheadvantageofsimpleinterfacecircuit,goodperformance,multi-effectsandeasytocontrol.Phaseaccumulator:Theroleofphaseaccumulatorsistolinearaccumulativetheinputfrequencycontrolword,throughfeedbackaclockonthestackinthebackoftheadderinputrealizeaccumulatefunction.Sothattheoutputeachclockcyclewillincreasek.Here,thenisthewordlengthofphaseaccumulators;thekiscalledfrequencycontrolword.Whenphaseaccumulatorsarefilledwithcanproduceaspill,thuscompletingacycle,thecycleisalsoacycleofDDS.IntheFig.3,thephaseaccumulatorsaremadebya32-bitadderanda32-bitregistersREG32.第8页Amongthem,VHDLcodeofthebinaryadderaddre32is:useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_unsigned.all;entityadder32isport(A:inSTD_LOGIC_VECTOR(31downto0);B:inSTD_LOGIC_VECTOR(31downto0);S:outSTD_LOGIC_VECTOR(31downto0);endadder32;architecturebhvofadder32isbegins=A+B;Endbhv;Inenvironment,choosethenewoffilemenu,selectCreateSymbolQuartsFilesforCurrentFileofCreateUpdateinnewwindow,thencompletesthecreationoftheproject.Inthedesignofschematicdiagram,clickthemouseleftkeydoubly,thenpopupSymboldialogbox,itcanfindandcallthe32-bitaddercreateintheProject.Tousethesamemethod,itcancreate32registersREG32.VHDLcodeis:libraryIEEE;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_unsigned.all;entityREG32isport(LOAD:inSTD_LOGIC;DIN:inSTD_LOGIC_VECTOR(31downto0);DOUT:outSTD_LOGIC_VECTOR(31downto0);endREG32;architecturebhvofREG32isbeginprocess(LOAD,DIN)begin第9页ifLOADeventandLOAD=1thenDOUT=DIN;endif;endprocess;Endbhv;Throughtheencapsulation,inthedesignoftheschematicdiagram,clickthemouseleftkeydoubly,itcanpopupSymboldialogbox.IntheProject,itcanfindandcallthe32registerstocreateREG32.ROMwavedata:BeforethedesignofwaveformgeneratoritmustbecompletedforthedesignoftheROMwavedata,usingmegawizardplug-inmanagercustomROMsignaldatamacromoduleandwilldesigngoodwavedataloadinginthisROM.FirstcreatemifdataformandthenIntheFilemenuselectnewandinthenewwindowchooseotherfilespage,thenchooseamemoryinitializationfile.ClicktheokbuttontoproducetheROMdatafilesizechoice.Inthedesign,choicetheROMdatanumberfor256anddatamodelswordissetto8-bit.Clicktheokbuttonanditwillappearemptymifdataformandcompilebythesoftwareandplacedcycle256pointwaveformdataofthetrianglewaveandsquarewaveandsinewave.Toselectthemegawizardplug-inmagerinthetoolsmenuandcreateanewcustominterface,thatis,anewcustommodule.ClicknextbuttonandcausetheLPMmacrofeaturepieceofsettingdialogboxandchoosetheLPM_ROMundertheleftcolumnstorage,finallyinputROMdepositpathandfilenameandfollowthepromptstoselecttheROMcontrollineandaddresslinesanddatalines.Finally,respectively,tri.mifandsqu.mifandsin.mifloadedintothewaveformmemoryinside.Waveforminmemoryofthecorrespondingisafunctionwaveformlookup,correspondingtodifferentphasecodevalueofoutputbydifferentcodevalue.Whenthephasecontrolwordis0,phaseaccumulateoutputsequenceisforthewaveformstorageaddressinganditwillgetaseriesofdiscreteamplitudeofthecode.TheamplitudecodedbytheD/Atransformationwillgetthecorrespondingladderwave,finally,smoothedbythelowpassfiltercanbeobtainedtheanalogwaveform.Phaseaccumulatorsundertimeandfrequencystandardsaction,carryonthelinearphaseaccumulate,whenphaseaccumulatorsfilledwith,itcanproduce第10页aspill,thuscompletingacycle,thecycleisalsoaDDSsignalfrequencycycle(HeandSun,2010).Lmp-mult1multiplier:Itsinputiswaveformandamplitudecontrolwordprocessed.Itsfunctionistoadjustthewaveformamplitude.Thelinemultiplicationaccumulatorsisasamacromodulestructure,itscallsandlmp_ROMcallsgeneralbasicmeetanditisshownFig.4.Fig.4:Lmp-mult1multiplierFig.5:WaveformselectorWaveformselector:Thepackagedselisawaveformchoicedevice.WhenpresstheswitchK1,theoutputisasinewave.WhenpresstheK2,theoutputisasquarewave.WhenpresstheK3,theoutputisatriangularwave.ItisshowninFig.5.TheVHDLcodeis:libraryIEEE;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_unsigned.all;entityselisport(K1,K2,K3:INSTD_LOGIC;sin_OUT,squ_OUT,tri_OUT:INSTD_LOGIC_VECTOR(9downto0);DOUT:outSTD_LOGIC_VECTOR(9downto0)第11页);endsel;architecturebhvofselissignalq:STD_LOGIC_VECTOR(9downto0);beginprocess(K1,K2,K3)beginifK1=0andK2=1andK3=1thenq=sin_OUT;-endif;ElseifK1=1andK2=0andK3=1thenq=squ_OUT;-endif;ElseifK1=1andK2=1andK3=0thenq=tri_OUT;-endif;-endif;endif;DOUT=q;Endprocess;endbhv;Fig.6:Interfaceof8051andDDSInterfaceofthemicrocontrollerandDDS:ThroughtheP0porttotheDDS,8051microcontrolleroutputsthesignalfrequencycontrolwordandthesignalamplitudecontrolword.LinkP33toenableterminalEN,whichisusedtocontroltheK8051exportcontrolthesignalword.WhentheenableterminalENis1,theoutputisafrequencycontrolword;whentheenableterminalEN第12页is0,theoutputisanamplitudecontrolword.BySWcomponents,thefrequencycontrolwordandphasecontrolwordwillbeoutputtedtotheDDSspecificlocation.ItisshowninFig.6.TheVHDLcodeis:libraryIEEE;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_unsigned.all;entityswisport(EN:inSTD_LOGIC;IN_word:inSTD_LOGIC_VECTOR(7downto0);Fword,Mword:outSTD_LOGIC_VECTOR(7Downto0);endsw;architecturebhvofswisbeginprocess(EN)beginif(EN=1)thenFword=IN_word;elseMword=IN_word;endif;endprocess;endbhv;DACtransformation:Eachdigitalcodehasthecertainbitrightvalue.Inordertoconvertdigitaltoanalog,thiscodeaccordingtothebitvalueoftherightmustbeconvertedintothecorrespondinganalogandthentheanalogsumcanbeobtainedwithdigitalproportionaltotheanalog,sothatitwillachievethedigital-analogconverter.第13页Fig.7:SinewavedisplayFig.8:SquarewavedisplayFig.9:TriangularwavedisplayVHDLcodeoftheDACis:libraryIEEE;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_unsigned.all;entityDACisport(CLK:inSTD_LOGIC;Q:inSTD_LOGIC_VECTOR(9downto0);-wr:outSTD_LOGIC;DOUT:outSTD_LOGIC_VECTOR(9downto0);endDAC;architecturebhvofDACis第14页beginprocess(CLK)beginifCLKeventandCLK=1thenDOUT=q;endif;-wr=0;endprocess;endbhv;Configurationfiledownloadandtest:Embeddedlogicanalyzertest,thewaveformofsine,squareandtriangularwaveisshowninFig.7,8and9.ThesoffilewillbecompiledintotheFPGA.Openprogrammingwindowandtheconfigurationfile.First,thetestsystemandparallelcommunicationlinesconnectedturnonthepower.Selectprogrammerinthetool,ifthefiledoesnoterror,clicktheaddfilebuttonontheleft,configuredfile8951.sofmanually.Chooseforprogrammingandclickonthedownloadpunctuationstartbutton,namelyintothetargetoftheFPGAdeviceconfigurationdownloadingoperations.softwareownsembeddedthelogicalanalyzercanQuartseffectivelyforthetestingofthesystemhardware.Inthetesting,SinnalTapIIsamplesignalmeasuredtemporarilystoredinthetargetdevicesembeddedRAMandthentheacquisitionsignalwillbesenttothecomputerfordisplayandanalysis(Luo,2011).OpenSinnalTapeditwindowandthencallthebeingmeasuredsignalandsetSinnalTapIIparameterandsavethefileandcompileanddownloadandfinallystartSinnalTapIItosampleandanalyzethesignal,atlastthecomputerdisplaysthisadjectivewaveform.5.CONCLUSIONThisstudytookFPGAassignalgenerator.FrequencyoramplitudevalueisinputfromthekeyboardanditwillbedisplayedintheLCD1602.FrequencyoramplitudevalueisconvertedtofrequencyoramplitudecontrolwordsenttotheDDSthroughthemicrocontroller.DDSrelyonthedeliveryfrequencyoramplitudecontrolword,theoutputwaveformforfrequencymodulationandfrequencymodulationprocessing.Thedirectnumericalfrequencysynthesizer第15页basedonFPGAhasalotofbenefits,suchasflexiblejoggleandwaytocontrol,relativelyshorttransmutingtime,relativelybroadbelt,thesuccessionofchangeofphasepositionandhighscreenresolution,etc.第16页中文翻译稿基于FPGA的数字波形发生器摘要:现场可编程门阵列(FPGA)的CycloneII系列是作为频率计的核心处理器,它以II为开发平台。本文设计了全数字信号发生器。它采用多尔数字频率合成Quarts技术及FPGA编程实现的三种波形:正弦波,方波和三角波。频率是可调的,通过10位相位累加器和模拟乘法器实现调幅。使用51软核的FPGA写了一个C程序,实现了在把控制字。44矩阵键盘
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