实验九 任意编码计数器的设计.doc

实验九 任意编码计数器的设计一、实验目的1、通过任意编码计数器体会语言编程设计电路的便利。2、了解状态机的设计原理。二、实验内容用状态机设计任意编码计数器，实现如下编码7进制计数器：0，2，5，3，4，6，1，并通过数码管显示。三、实验原理状态转移图四、引脚分配情况：下表为GX-SOC/SOPC-EP2C35-M672创新开发实验平台引脚分配建议表设计端口芯片引脚开发平台模块out0AE13HEX_1Aout1AF13HEX_1Bout2AD12HEX_1Cout3AE12HEX_1Dout4AA12HEX_1Eout5Y12HEX_1Fout6V11HEX_1GclkP2550M 主时钟rstF6SW1A五、实验报告要求实验报告上要体现系统的设计过程，包括所有的代码、仿真结果和硬件验证结果。library IEEE; -get 1HZ use IEEE.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dividef is port ( CLK : in std_logic; CLK_D: out std_logic );end entity;architecture DIVIDE_arch of dividef issignal COUNT : integer range 0 to 50000000;begin PROCESS(CLK) BEGIN if clkevent and clk=1 then IF COUNT=50000000 then COUNT=0; ELSE COUNT=count+1; END IF; END IF; END PROCESS;PROCESS(COUNT)BEGIN IF COUNT=50000000 THEN CLK_D=1; ELSE CLK_Dd=000;if reset=1then next_state=s1;else next_stated=010;if reset=1then next_state=s1;else next_stated=101;if reset=1then next_state=s1;else next_stated=011;if reset=1then next_state=s1;else next_stated=100;if reset=1then next_state=s1;else next_stated=110;if reset=1then next_state=s1;else next_stated=001;if reset=1then next_state=s1;else next_state=s2;end if;end case;end process;process(clk)beginif clk=1and clkevent thencurrent_state=next_state;end if;end process;end xsb1_arch;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity seg7 is port(indata: in std_logic_vector(3 downto 0); outdata: out std_logic_vector(0 to 6);end seg7;architecture behavior of seg7 is begin with indata select outdata=1111110 when 0000, 0110000 when 0001, 1101101 when 0010, 1111001 when 0011, 0110011 when 0100, 1011011 when 0101, 1011111 when 0110, 1110000 when 0111, 1111111 when 1000, 1111011 when 1001,