verilog--串并转换.doc

Verilog作业 姓名：zzz 班級： zzzz 學號：zzzz報告日期：2010年10月30日作业题目要求：实现8位的并行数据转换为串行的数据。题目分析：并行转串行，只要把每个输入按从高到低的顺序输出即可。即每个时钟脉冲输出一个数据。但是下面的代码有一个的问题，不能解决在8为数据串行输出的过程当中如果又有一个并行的输入数据输入，没有做到缓冲处理。也许这个缓冲处理可以在调用此模块时在外部实现吧。功能代码：module para_to_serial_8bit(para_in,clock,reset,ser_out); input 7:0 para_in; input reset,clock; output ser_out; reg ser_out; reg 7:0 data; always(posedge clock or negedge reset) begin if(reset) begin ser_out = 1b0; data = para_in; end else begin data = data6:0,data7; ser_out = data7; end endendmodule测试代码：module test_para_to_ser; reg 7:0 para_in; reg clock,reset; wire out; para_to_serial_8bit f1(.para_in(para_in),.clock(clock),.reset(reset),.ser_out(out); initial $monitor($time,in_8bit = %b,reset= %b,ser_out= %b,data=%b,para_in,reset,out,f1.data); initial begin clock = 1b0; reset = 1b0; #3 reset = 1b1; #300 $stop; end initial para_in = 8b1010_0100; always #5clock = clock;endmodule测试结果：测试波形如下：作业二题目要求：实现8位的串行数据转换为并行的数据。题目分析：8位串行数据转换为并行数据，需要一个模为8的计数器，当计到8个时钟脉冲时，把之前的8个数据全部输出，然后从新接收。功能模块代码：模8计数器：module counter_mod_8(clock,reset,Q); input clock; /posedge effective input reset; / negedge effective output 2:0 Q; reg 2:0 Q; always(posedge clock or negedge reset) begin if(reset) Q = 3d0; else Q = Q + 1; endendmodule串转并模块：module ser_to_par_8bit(ser_in,clk,rst,out); input ser_in,clk,rst; output 7:0 out; wire 7:0 out; reg 7:0 par_out; wire 2:0 count; counter_mod_8 f1(.clock(clk),.reset(rst),.Q(count); always(posedge clk or negedge rst) begin if(rst) par_out = 8b0000_0000; else begin par_out = par_out6:0,ser_in; end end assign out = (count = 7)? par_out : 8b0000_0000;endmodule测试模块代码：module test_ser_par; reg 7:0 data; wire data_in; reg clock, reset; wire 7:0 out; initial begin clock = 1b0; reset = 1b0; #3 reset = 1b1; data = 8b1001_1101; #300 $stop; end always #5clock = clock; always(posedge clock) data =data6:0,data7; assign data_in = data7; ser_to_par_8bit a(.ser_in(data_in),.clk(clock),.rst(reset),.out(out); initial $monitor($time,reset= %b,data= %b,data_in= %b,out= %b,reset,data,data_in,out);endmodule测试结果：测试波形：作业三题目：可变模计数器，当控制信号为1时，模值为16，当控制信号为0是模值为32。功能模块代码：/ contr = 1 mod =16; contr =0 mod =32module count_mod_chg(clk,reset,contr,Q); input clk,reset,contr; output 4:0 Q; reg 4:0 Q; wire 4:0 last; assign last =(contr ? 5b01111:5b11111); always(posedge clk or negedge reset) begin if(reset | Q = last) Q = 5b00000; else Q = Q + 1; end endmodule测试模块代码：module test_count_mod_chg; reg clock,reset; reg control; wire 4:0 out; count_mod_chg counter1(.clk(clock),.reset(reset),.contr(control),.Q(out); initial $monitor($time,reset= %b,control= %b,out= %b,reset,control,out); initial begin clock = 1b0; foreve