电子音乐发生器soc实验报告.docx

电子音乐发生器设计实验报告 一 实验要求1. 2种电子音乐播放模式的自动循环播放。2. 手动选择某一模式的循环播放。3. 数码管显示该播放模式。二 工作原理1）简谱中音名所对应的频率（HZ）如下表所示音名频率音名频率音名频率低音1261.1中音1523.3高音11045.5低音2293.7中音2587.3高音21174.7低音3392.6中音3659.3高音31318.5低音4349.2中音4698.5高音41396.9低音5392中音5784高音51568低音6440中音6880高音61760低音7493.9中音7987.8高音71785.52）音阶频率的获得 由硬件实验装置的晶振频率经过适当的分频系数和输出音频整形（对称方波）就可以得到音阶频率。 为了使输出的频率为对称的方波，故在分频系数计算时要除以2，在最后输出到交流蜂鸣器前要进行将输出频率二分频恢复原音名频率。例如以10M为基准频率，要将低音3频率为392.6hz音频信号送出。 假设硬件实验的晶振频率为10M，则： 分频系数K=（10M/392.6）/2=12736将10M基准频率进行12736分频得到的是低音3频率的倍频信号392.6*2=592.4hz. 在输出到交流蜂鸣器前再将592.4hz进行2分频得到的是392.6hz低音3对称方波信号的频率。3）节拍控制器 乐曲节拍1拍定义为1秒，2/8拍为0.25秒以此类推，根据节拍将所编辑的音乐输出到交流蜂鸣器。一般以一首曲的最低节拍为基准节拍。基准节拍可通过分频电路获得。4）乐曲输入模块根据所选乐曲将简谱转换成频率信号，根据节拍输出乐曲频率信号。三 实验步骤初步设计：由设计流程图画出顶层原理图草稿。模块设计和调试：设计各个模块。对每一模块进行功能仿真，验证其逻辑或时序是否符合设计要求。总体设计调试：完成时钟设计顶层原理。根据所选芯片型号，定义LOG,进行设计实现调试。硬件验证：将程序通过数据电缆由电脑下载到芯片，在演示板上进行设计功能硬件验证。四 设计方框图 五 实验电路图六 实验程序 1）音频控制器ypkz2:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity ypkz2 is Port ( clk : in STD_LOGIC; en : in STD_LOGIC; ch : in STD_LOGIC; btype : out STD_LOGIC_VECTOR (3 downto 0); ypfp : out STD_LOGIC_VECTOR (4 downto 0);end ypkz2;architecture folow of ypkz2 issignal a:integer range 0 to 334;signal c:integer range 0 to 334;signal b:std_logic_vector(1 downto 0);type memory is array(0 to 167) of integer range 0 to 21;signal ROM1: memory;signal ROM2: memory;beginROM1=(10,9,10,12,13,12,15,13, 12,10,12,12,12,12,13,13, 15,15,16,17,16,15,13,15, 12,12,12,12,0,0,0,0, 12,12,10,10,12,12,13,13, 15,15,16,17,15,13,12,12, 12,12,9,9,10,12,10,9, 8,6,8,8,8,8,0,0, 10,9,8,8,9,9,0,10, 12,12,13,15,13,13,12,12, 12,12,10,9,10,12,10,9, 8,9,6,6,6,6,8,8, 9,9,0,10,8,9,8,6, 8,6,5,5,5,5,0,0, 10,9,8,8,9,9,0,10, 12,12,13,15,13,13,12,12, 12,10,9,9,10,12,10,9, 8,9,6,6,6,6,8,8, 16,16,0,17,15,16,15,13, 12,13,15,17,16,15,13,15, 12,12,12,12,0,0,0,0);ROM2=( 17,17,0,16,16,16,16,17, 15,15,0,0,0,0,0,0,12,12,8,8,13,12,10,10,12,12,0,0,0,0,0,0,12,12,12,13,15,15,8,15,13,13,15,15,10,10,0,0,12,12,12,13,12,12,10,9,9,9,0,0,0,0,0,0,17,17,0,0,16,16,16,17,15,15,0,0,0,0,0,0,10,10,15,15,13,12,10,10,12,12,0,0,0,0,0,0,12,12,12,13,15,15,15,15,13,13,12,13,10,10,0,10,17,17,17,17,17,17,16,13,8,8,0,0,0,0,0,0,15,15,0,0,14,14,13,14,10,10,0,0,0,0,0,0,12,12,12,13,13,0,10,9,9,9,0,0,0,0,0,0,10,10,0,12,13,13,13,13);process(clk,c)beginif rising_edge(clk) thenif a=c then a=0;elsea=a+1;end if;end if;end process ;PROCESS( clk,a,en,ch1)beginb=en&ch1;if rising_edge(clk) thenif b=10 then btype=0001; c=167;ypfp=conv_std_logic_vector(ROM1(a),5);elsif b=11 then btype=0010;c=167;ypfp=conv_std_logic_vector(ROM2(a),5);elsebtype=ZZZZ;ypfp=00000;end if;end if;END process ;end folow;2)分频器fp1_4library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity fp1_4 is Port ( clk : in STD_LOGIC; cp : out STD_LOGIC);end fp1_4;architecture Behavioral of fp1_4 issignal a:integer range 0 to 20000000;beginprocess(clk)beginif rising_edge(clk) thenif a=1249999 thena=0;else acpcpcp=Z;end case;end if;end process;end Behavioral;3)节拍控制器ypfp:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity ypfp is Port ( clk : in STD_LOGIC; datafp : in STD_LOGIC_VECTOR (4 downto 0); cp : out STD_LOGIC);end ypfp;architecture Behavioral of ypfp issignal a:integer range 0 to 10000;signal b:integer range 0 to 10000;signal pclk,pulse:std_logic:=0;beginprocess(clk)beginif rising_edge(clk) thena=a+1;if a=b thena=0;pulse=1;elsepulse=0;end if;end if;end process;process(pulse)beginif rising_edge(pulse)thenpclk b b b b b b b b b b b b b b b b b b b b b b=0; end case;end process ;cp=pclk; end Behavioral;4)解码器decode:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity decode_1 is Port ( en : in STD_LOGIC; q : in STD_LOGIC_VECTOR (3 downto 0); x : out STD_LOGIC_VECTOR (6 downto 0); d : out STD_LOGIC_VECTOR (2 downto 0);end decode_1 ;architecture Behavioral of decode_1 isbeginprocess(en,q)beginif en=0 thenx=0000000;d=101;elsedxxxx=0000000;end case;end if;end process;end Behavioral;5)2分频器twofp:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity twopf is Port ( en : in STD_LOGIC; clk : in STD_LOGIC; cp : out STD_LOGIC);end twopf;architecture Behavioral of twopf issignal a:std_logic:=0;beginprocess(en,clk)beginif en=0 thena=0;elsif rising_edge(clk) thena=not a;end if;cp=a;end process;end Behavioral;4.按键接口cp output p17ch1 input p23clk0 input p125d output p76d output p77d output p78en input p20x output p73x output p70x output