电气093-200909241-刘永元英文文献 - 英文

兰州交通大学毕业设计英文翻译（英文）毕业设计英文翻译（原文） 专 业 电气工程及其自动化 姓 名 刘 永 元 学 号 200909241 指导教师 赵 峰 李 红 FPGA-Based All Digital Phase-Locked Loop Controlled Induction Heating Power Supply Operating at Optimized ZVS ModeHeming LI, Yabin LI, Yonglong PENG Department of Electrical Engineering, North China Electric Power University, Baoding 071003, ChinaAbstract-This paper introduces a new induction heating power supply, whose rectifier is a three-phase buck-type rectifier modulated with space vector PWM method (SVPWM)and the full-bridge series-resonant inverter is controlled by an all digital phase-locked loop operating at optimized ZVS mode. All the control circuits including SVPWM generator for rectifier, all digital phase-locked loop for resonant inverter and other functions are realized on one chip Field Programmable Gate Array (FPGA). The advantages of the developed system are nearly unity power factor in ac supply currents, accurate phase locking at high resonant frequency and low power losses of switching IGBTs. The theory analysis and modeling method about the system are introduced as well as the control scheme and implementation based on FPGA. It is proved from experiments that the developed power supply, using all digital technique, has very high reliability, good dynamic and static performances.I. INTRODUCTIONHigh-frequency induction heating power supplies are widely used in applications such as surface hardening,welding, metal to plastic or metal to glass bonding and curing. The high efficiency, short heating times and local heating capabilities have made them superior to other heating devices. In order to minimize the switching loss and increase the efficiency of resonant inverter, zero-currentswitching (ZCS) or zero-voltage-switching (ZVS) conditions should be achieved generally using phase-locked loop control circuit. There are many different control schemes such as asymmetrical voltage-cancellation control introduced in literature 1, phase-shift or clamped-mode control in literature 2-3. However, almost all the inverter control circuits are implemented with phase-locked loop integrated circuit (PLL-IC), which is comprised of special IC and analog components. It is well known that the analog circuits are sensitive to temperature and electromagnetic noise, disadvantages that make the control circuit difficult to design, low flexible and low accuracy. Literature 4 proposed a DSP-based PLL-controlled technique. However,it also consists of analog components. And due to the sequential software structure of DSP, it is very difficult to make the software PLL working at frequency more than 1OOkHz. Compared with DSP, FPGA has superiority of very high speed due to its parallel operation structure and plenty of logic resources that can be configured flexibly. So,literature 5 introduced an all-digital PLL implemented with FPGA, which is suitable for high frequency resonant inverter control circuit.II. SYSTEM DESCRIPTIONThe circuit diagram of present induction heating power supply including control system implemented with FPGA is shown in figure 1. Each power semiconductor switch of the buck type rectifier consists of an IGBT connected in series with an ultra-fast recovery diode, resulting in reverse voltage blocking capability and unidirectional current flow.A low pass LC filter is connected to the input side of the rectifier to filter out the switching frequency harmonics in the line current of ac power supply. The inductor Ld that feeds the dc bus acts as a stiff current source. Since the buck type rectifier acts as a voltage source for the series-resonant inverter, a parallel Connection of dc capacitor Cd is needed across the dc bus. It is noted that the additional freewheeling diode Dw is not indispensable in the system. However, on the aspect of safety and reducing switching losses of IGBTs of rectifier, a freewheeling diode is suggested to be used to avoid device damage caused by error trigger and IGBT broken.The full-bridge resonant inverter is composed of 4 IGBTs(SI -S44) with inner parallel connected ultra-fast recovery diode (DI1-D44). The capacitor CH, equivalent inductor LH and resistant RH make up of the resonant load. The signal IH,Id, Ud, is the load current, dc current and dc voltage feedback signal for control, protection and display,respectively. And Ud* is the referent dc voltage to control the output power of the system.Figure 1. The circuit diagram of the induction heating power supplyIn this work, the SVPWM rectifier control part, as well as the inverter control part and other functions are all realized on one chip FPGA ( Xilinx Spartant II 2s200 ), which can fulfill the whole control functions.III. RESONANT INVERTER CONTROL CIRCUITA. Principle and implementation ofthe all digital PLLThe detailed principle and implementation of all digital PLL based on FPGA is proposed in literature 5, whose phase detector is a JK trigger. In order to achieve optimized ZVS control scheme, a phase-edge detector is needed. The whole schematic diagram of the proposed all digital PLL is shown in figure 2, and the time sequences of signals are shown in figure 3, from which the design of the all digital PLL realized by FPGA can be achieved.Figure 2. The schematic diagram of self-sampling PI control allDigital phase-locked loop Figure 3. Operation waveforms of the self-sampling PI control alldigital phase-locked loopThe linearization transfer function is obtained as 5. (1) (2) (3)where ft, k , ki, k, J, W is the frequency of tracked signal, proportional coefficient, integral coefficient, K-filter number, damping coefficient and local resonant angular frequency of the close loop, respectively.From equations (1-3), one can find that the transfer function of proposed all digital PLL is a typical 2-ordersystem, whose damping coefficient is determined just by the control parameters and local resonant angular frequency is determined by the frequency of tracked signal in addition, a new characteristic of the proposed all digital PLL that can make the tracking speed proportional to the tracked signal.The all digital PLL has fast locking speed and is insensitive to the outside interferences. Its locking duration is about 5. (4)And its phase locking error is about, (5)Where fo is the clock frequency of FPGA.B. Optimized ZVS control schemeIt is difficult to determine the accurate optimized switching point of the resonant inverter theoretically due to the non-linear characteristics of semiconductors, various absorber circuits, parasitical parameters of line and the very short switching time. The most effective method maybe is to test different schemes through experiments. So, the purpose of optimized ZVS control scheme in this paper is to find the tendency of optimized ZVS point and then make the PLL operate close to it.The simplified switching states of resonant inverter are shown in figure 4.From detailed analysis of the switching modes, one can draw the important conclusion that the charge of the absorb capacitors, including the junction capacitance of switches, should be charged or discharged completely during thedead-time period if the ZVS condition is to be maintained.And, the time point when the capacitances just have charged and discharged completely, is the optimized ZVS switching point. It is clearly that the optimized switching point locates at the dead-time boundary. Through this way, not only the ZVS condition can be fit, but also the turned off current is minimized, which can minimize the power losses of turned off switches.Figure 4. Switching states of resonant inverter, (a) non-ZVS stateThe total charge of absorber capacitances duringcommutating period is (6)And the charge that can be drawn by load current is, (7)When the optimized ZVS mode has to be met ,the following equations should be satisfied, (8) (9) (10)where C is the absorber capacitance of each switch, Ud is the dc voltage, m is the amplitude value of resonant load current, and time points are shown in figure 4.The all digital PLL can dynamically change the innerloop time delay according to the sampled value of Ud, Id and working frequency, realized by a fuzzy logic controller, to track the optimized switching point.IV. SIMULATIONS AND EXPERIMENTSBased on the analysis above, the simulation model of whole system is built based on Matlab/Simulink. The simulation results are shown in figure 5, 6. Figure 7, 8, 9 are the experimental results. The parameters in experiments are set as: vs=60 V, Labc=0.48 mH, Cabc=45 uF, Ld=8.4 mH,Cd=470 uF, LH=143 uH-75 uH (changeable), RL=10 ohm-7.5 ohm (changeable), CH=0.033 uF, Rabsorb=3 ohm,Figure 5. Resonant current and voltage at optimized ZVS mode Figure 6. Resonant current and voltage at non-ZVS Figure 7. Load current and output voltage when the load RH changing from 7.5 ohm to 10 ohm at about 93 kHz, (50V/div1OA/div.I Ous/div.). From top to bottom IH and UH, voltage of switched loadFigure8 Load current and output voltage working at134.2kHz (50V/div., 1OA/div., 2.5us/div.). From figure 5、6, one can find that the operation conditions of the semiconductors under optimized ZVS mode are superior to that under non-ZVS mode, although the resonant power factor of figure 6 under non-ZVS mode is unity. And, the power losses of switches under optimized ZVS are also reduced.Figure 7 shows the dynamic frequency trac