MIPI 协议详细介绍ppt课件

MIPIProtocolIntroduction MIPIDevelopmentTeam2010 9 2 WhatisMIPI MIPIstandsforMobileIndustryProcessorInterfaceMIPIAllianceisacollaborationofmobileindustryleaders Objectivetopromoteopenstandardsforinterfacestomobileapplicationprocessors IntendstospeeddeploymentofnewservicestomobileusersbyestablishingSpec BoardMembersinMIPIAllianceIntel Motorola Nokia NXP Samsung ST TI WhatisMIPI MIPIAllianceSpecificationfordisplayDCS DisplayCommandSet DCSisastandardizedcommandsetintendedforcommandmodedisplaymodules DBI DPI DisplayBusInterface DisplayPixelInterface DBI Parallelinterfacestodisplaymoduleshavingdisplaycontrollersandframebuffers DPI Parallelinterfacestodisplaymoduleswithouton paneldisplaycontrollerorframebuffer DSI CSI DisplaySerialInterface CameraSerialInterface DSIspecifiesahigh speedserialinterfacebetweenahostprocessoranddisplaymodule CSIspecifiesahigh speedserialinterfacebetweenahostprocessorandcameramodule D PHYD PHYprovidesthephysicallayerdefinitionforDSIandCSI DSILayers DCSspec DSIspec D PHYspec Outline D PHYIntroductionLaneModule StateandLinelevelsOperatingModesEscapeModeSystemPowerStatesElectricalCharacteristicsSummary IntroductionforD PHY D PHYdescribesasourcesynchronous highspeed lowpower lowcostPHYAPHYconfigurationcontainsAClockLaneOneormoreDataLanesThreemainlanetypesUnidirectionalClockLaneUnidirectionalDataLaneBi directionalDataLaneTransmissionModeLow Powersignalingmodeforcontrolpurpose 10MHz max High Speedsignalingmodeforfast datatraffic 80Mbps 1GbpsperLaneD PHYlow levelprotocolspecifiesaminimumdataunitofonebyteAtransmittershallsenddataLSBfirst MSBlast D PHYsuitedformobileapplicationsDSI DisplaySerialInterfaceAclocklane Onetofourdatalanes CSI CameraSerialInterface TwoDataLanePHYConfiguration LaneModule PHYconsistsofD PHY LaneModule D PHYmaycontainLow PowerTransmitter LP TX Low PowerReceiver LP RX High SpeedTransmitter HS TX High SpeedReceiver HS RX Low PowerContentionDetector LP CD ThreemainlanetypesUnidirectionalClockLaneMaster HS TX LP TXSlave HS RX LP RXUnidirectionalDataLaneMaster HS TX LP TXSlave HS RX LP RXBi directionalDataLaneMaster Slave HS TX HS RX LP TX LP RX LP CD UniversalLaneModuleArchitecture LaneStatesandLineLevels ThetwoLP TX sdrivethetwoLinesofaLaneindependentlyandsingle ended FourpossibleLow PowerLanestates LP 00 LP 01 LP 10 LP 11 AHS TXdrivestheLanedifferentially TwopossibleHighSpeedLanestates HS 0 HS 1 DuringHStransmissiontheLPReceiversobserveLP 00ontheLinesLineLevels typical LP 0 1 2VHS 100 300mV Swing 200mV LaneStatesLP 00 LP 01 LP 10 LP 11HS 0 HS 1 OperatingModes TherearethreeoperatingmodesinDataLaneEscapemode High Speed Burst modeandControlmodePossibleeventsstartingfromtheStopStateofcontrolmodeEscapemoderequest LP 11 LP 10 LP 00 LP 01 LP 00 High Speedmoderequest LP 11 LP 01 LP 00 Turnaroundrequest LP 11 LP 10 LP 00 LP 10 LP 00 EscapeMode EscapemodeisaspecialoperationforDataLanesusingLPstates Withthismodesomeadditionalfunctionalitybecomesavailable LPDT ULPS TriggerADataLaneshallenterEscapemodeviaLP 11 LP 10 LP 00 LP 01 LP 00OnceEscapemodeisentered thetransmittershallsendan8 bitentrycommandtoindicatetherequestedaction EscapemodeusesSpaced One HotEncoding meanseachMarkStateisinterleavedwithaSpaceState LP 00 SendMark 0 1followedbyaSpacetotransmita zero bit one bit ADataLaneshallexitEscapemodeviaLP 10 LP 11Ultra LowPowerStateDuringthisstate theLinesareintheSpacestate LP 00 ExitedbymeansofaMark 1statewithalengthTWAKEUP 1ms followedbyaStopstate EscapeMode ClockLaneUltra LowPowerState AClockLaneshallenterULPSviaLP 11 LP 10 LP 00exitedbymeansofaMark 1withalengthTWAKEUPfollowedbyaStopStateLP 10 TWAKEUP LP 11TheminimumvalueofTWAKEUPis1ms High SpeedDataTransmission Theactionofsendinghigh speedserialdataiscalledHStransmissionorburst Start of TransmissionLP 11 LP 01 LP 00 SoT 0001 1101 HSDataTransmissionBurstAllLaneswillstartsynchronouslyButmayendatdifferenttimesTheclockLaneshallbeinHigh Speedmode providingaDDRClocktotheSlavesideEnd of TransmissionHTogglesdifferentialstateimmediatelyafterlastpayloaddatabitandkeepsthatstateforatimeTHS TRAIL High SpeedClockTransmission SwitchingtheClockLanebetweenClockTransmissionandLPModeAClockLaneisaunidirectionalLanefromMastertoSlaveInHSmode theclockLaneprovidesalow swing differentialDDRclocksignal theClockBurstalwaysstartsandendswithanHS 0state theClockBurstalwayscontainsanevennumberoftransitions SummaryforD PHY LaneModule LaneStateandLineLevelsLaneModule LP TX LP RX HS TX HS RX LP CDLaneStates LP 00 LP 01 LP 10 LP 11 HS 0 HS 1LineLevels typical LP 0 1 2V HS 100 300mV Swing 200mV OperatingModesEscapeModeentryprocedure LP 11 LP 10 LP 00 LP 01 LP 00 EntryCode LPD 10MHz EscapeModeexitprocedure LP 10 LP 11HighSpeedModeentryprocedure LP 11 LP 01 LP 00 SoT 00011101 HSD 80Mbps 1Gbps HighSpeedModeexitprocedure EoT LP 11ControlMode BTAtransmissionprocedure LP 11 LP 10 LP 00 LP 10 LP 00ControlMode BTAreceiveprocedure LP 00 LP 10 LP 11SystemPowerStatesLow Powermode High Speedmode Ultra LowPowermodeFaultDetectionContentionDetection LP CD WatchdogTimer SequenceErrorDetection ErrorReport GlobalOperationTimingParameterClockLaneTiming DataLaneTimingOtherTiming Initialization BTA Wake UpfromULPSElectricalCharacteristicsHS RX LP RX LP TX LP CD Pincharacteristic Clocksignal Data ClocktimingDCandACcharacteristic Outline DSIIntroductionLaneDistributor MergerConceptualPacketStructureDataTransmissionWayProcessor SourcedPacketsPeripheral SourcedPacketsReverse DirectionLPTransmissionVideoModeSummary IntroductionforDSI DSIisaLane scalableinterfaceforincreasedperformance OneClockLane OnetoFourDataLanesDSI compliantperipheralssupporteitheroftwobasicmodesofoperationCommandMode SimilartoMPUIF DataLane0 bidirectionalForreturningdata ACKorerrorreporttohostAdditionalDataLanes unidirectional VideoMode SimilartoRGBIF DataLane0 bidirectionalorunidirectional AdditionalDataLanes unidirectional VideodatashouldonlybetransmittedusingHSmode TransmissionModeHigh SpeedsignalingmodeLow PowersignalingmodeForward ReversedirectionLPtransmissionsshalluseDataLane0onlyForreturningdata DSI compliantsystemsshallonlyuseDataLane0inLPModePacketTypesShortPacket 4bytes fixedlength LongPacket 6 65541bytes variablelength TwoDataLanesHSTransmissionExample DataTransmissionWay SeparateTransmissions SeparateTransmissions KEY LPS LowPowerStateSP ShortPacketSoT StartofTransmissionLgP LongPacketEoT EndofTransmission ShortPacketStructure PacketHeader 4bytes DataIdentifier DI 1byte ContainstheVirtualChannel 7 6 andDataType 5 0 PacketData 2byte LengthisfixedattwobytesErrorCorrectionCode ECC 1byte allowssingle biterrorstobecorrectedand2 biterrorstobedetected PacketSizeFixedlength4bytesThefirstbyteofanypacketistheDI DataIdentifier byte DI 7 6 Thesetwobitsidentifythedataasdirectedtooneoffourvirtualchannels DI 5 0 ThesesixbitsspecifytheDataType LongPacketStructure PacketHeader 4bytes DataIdentifier DI 1byte ContainstheVirtualChannel 7 6 andDataType 5 0 WordCount WC 2byte definesthenumberofbytesintheDataPayload ErrorCorrectionCode ECC 1byte allowssingle biterrorstobecorrectedand2 biterrorstobedetected DataPayload 0 65535bytes Length WC bytesPacketFooter 2bytes ChecksumIfthepayloadhaslength0 thentheChecksumcalculationresultsinFFFFhIftheChecksumisn tcalculated theChecksumvalueis0000hPacketSize4 0 65535 2 6 65541bytes DataTypesforProcessor sourcedPackets ErrorCorrectionCode P7 0P6 0P5 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D21 D22 D23P4 D4 D5 D6 D7 D8 D9 D16 D17 D18 D19 D20 D22 D23P3 D1 D2 D3 D7 D8 D9 D13 D14 D15 D19 D20 D21 D23P2 D0 D2 D3 D5 D6 D9 D11 D12 D15 D18 D20 D21 D22P1 D0 D1 D3 D4 D6 D8 D10 D12 D14 D17 D20 D21 D22 D23P0 D0 D1 D2 D4 D5 D7 D10 D11 D13 D16 D20 D21 D22 D23 Checksum unsignedcharxx 0 x01 0 x5a 0 x5a 0 x03 0 x08 0 x2A 0 x00 0 x01 0 x00 0 xF8 0 x00 0 xF6 0 x57 0 x00 0X00 0 xE5 typedefunsignedshortU16 typedefunsignedcharU8 U16CRC test U16crc16 update U16crc U8a intmain U16crc i crc 0 xFFFF for i 0 i 1 i crc crc16 update crc xx i CRC test crc U16crc16 update U16crc U8a inti crc a for i 0 i 1 0 x8408 elsecrc crc 1 returncrc Peripheral to ProcessorLPTransmissions DetailedformatdescriptionPacketstructureforperipheral to processortransactionsisthesameasfortheprocessor to peripheraldirectionForasingle bytereadresponse validdatashallbereturnedinthefirstbyteThesecondbyteshallbesentas00hIftheperipheraldoesnotsupportChecksumitshallreturn0000h Peripheral to ProcessorLPTransmissions Peripheral to processortransactionsareoffourbasictypesTearingEffect TE triggermessage BAh Acknowledge triggermessage 84h AcknowledgeandErrorReport shortpacket DataTypeis02h ResponsetoReadRequest shortpacketorlongpack