vhdl 2位十进制计算器实验报告（完成版）.doc

简易计算器设计电信082班 （合作者：电信082班）指导教师： 2010-6-23（目录）1、 设计要求与计数指标-（1）2、 实验方案-（1）3、 系统软件设计-（1）4、 系统调试-（7）5、 附录一-（8）1 设计任务与要求(或技术指标)1.1 设计任务： 简易计算器设计1.2 技术指标： 1）实现最大输入两位十进制数字的四则运算（加减乘除） 2）能够实现多次连算（无优先级，从左到右计算结果） 3）如 12+3456-7890+9=36.75 4）最大长度以数码管最大个数为限，溢出报警 5）有正负数区分 6）除法不能除尽时小数保留2位有效数字2 方案 用基于Quartus II的CPLD,FPGA方法实现。3系统软件设计 1)输入控制器模块： library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity anjian isport( qiehuan,mai_s,mai_f,shu1,shu0,fuhao_in,clear,ok: in std_logic; shu_show: out unsigned(7 downto 0); fuhao_out:out unsigned(1 downto 0); fuhao_show:out unsigned(1 downto 0); shu_suan:out unsigned(7 downto 0) );end anjian;architecture behave of anjian issignal shu_1,shu_0:unsigned(3 downto 0);signal fuhao:unsigned(1 downto 0);begin process(qiehuan,mai_s,mai_f,shu1,shu0,fuhao_in,clear,ok)begin if(clear=0)then shu_1=0000;- else if(fuhao_in event and fuhao_in=1)then fuhao=fuhao+1; end if; if(shu1 event and shu1=1)then if(shu_1=9)then shu_1=shu_1-9; else shu_1=shu_1+1; end if; end if; if(shu0event and shu0=1)then if(shu_0=9)then shu_0=shu_0-9; else shu_0=shu_0+1; end if; end if; shu_show=shu_1&shu_0; fuhao_show=fuhao; if(mai_s event and mai_s=1)then shu_suan=shu_1*1010+shu_0; end if; if(mai_f event and mai_f=1)then fuhao_out=fuhao; end if; end if;end process;end behave; entity anjian2）运算器（实现加法、减法、除法）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity yunsuan isport( fuhao_in: in unsigned( 1 downto 0); shu_suan:in unsigned(7 downto 0); clear: in std_logic; shu_answer: out unsigned(35 downto 0); chuf_en: out std_logic; zhengf_out:out std_logic; entity yunsuan answer_in: in unsigned(35 downto 0); -error:out std_logic; ok:in std_logic; mai_s:in std_logic);end yunsuan;-architecture behave of yunsuan issignal fuhao:unsigned( 1 downto 0);signal shu :unsigned( 7 downto 0);shared variable answer: unsigned(35 downto 0);signal zhengf:std_logic:=0;shared variable shu_suan1:unsigned(14 downto 0);signal chengf:unsigned(43 downto 0);beginprocess(fuhao_in,shu_suan,mai_s)begin if(clear=0)then answer:=000000000000000000000000000000000000 ;zhengf if(zhengf=1)then -answer 为负 if(answer_inshu_suan1)then zhengf=1;answer:=answer_in-shu_suan1; else answer:=shu_suan1-answer_in; zhengf=0; end if; else answer:=shu_suan1+answer_in;zhengf=0; end if; chuf_en if(zhengf=0)then -answer 为正 if(answer_inshu_suan1)then zhengf=0;answer:=answer_in-shu_suan1; else answer:=shu_suan1-answer_in; zhengf=1; end if; else answer:=shu_suan1+answer_in;zhengf=1; end if; chuf_en chengf=answer_in*shu_suan;answer:=chengf(35 downto 0);chuf_enanswer:=answer_in;chuf_enanswer:=000000000000000000000000000000000000 ;chuf_en=0; end case; end if;end if;shu_answer=answer;zhengf_out100000000)end process;end behave;3） 调用系统中已有的除法运算模块 4）加减乘的结果或除法的运算结果选择模块 由选择得到本次运算的最终结果library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity chufa isport( answer_in,chuf_in:in unsigned(35 downto 0); entity chufa answer_out: out unsigned(35 downto 0); chuf_en: in std_logic; error_out:out std_logic);end chufa;architecture behave of chufa is-signal temp1,temp2,temp3:std_logic;signal answer_o: unsigned(35 downto 0);beginprocess(answer_in,chuf_in,chuf_en)begin if(chuf_en=1)then answer_o=chuf_in; else answer_o99999999)then error_out=1; else error_out=0; end if; answer_out=answer_o; -if(chuf_enevent and chuf_en=1)then - temp1=chuf_en; - temp2=temp1; - temp3=temp2; -end if; -huiz_out=(not temp1) and temp2 and temp3; -if fcevent and fc=1 then - temp1=fm; - temp2=temp1; - temp3=temp2;-end if; -sc=(not temp1) and temp2 and temp3;end process;end behave;5）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity shuma_controll isport(qiehuan:in std_logic; shu_show:in unsigned(7 downto 0); fuhao_show:in unsigned(1 downto 0); answer:in unsigned(31 downto 0); entity shuma_controll pout:out unsigned(31 downto 0);end shuma_controll;architecture behave of shuma_controll isbeginprocess(qiehuan,shu_show,fuhao_show,answer)beginif(qiehuan=1)then pout=answer; elsif(qiehuan=0)then pout=00&fuhao_show&00000000000000000000&shu_show;end if;end process;end behave;6）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity combine isport(p0,p1,p2,p3,p4,p5,p6,p7:unsigned(3 downto 0); q:out unsigned(31 downto 0); end combine;architecture behave of combine isbeginprocess(p0,p1,p2,p3,p4,p5,p6,p7) entity combinebe